A generalized framework for energy savings in hard real-time embedded systems

IPSJ Transactions on System LSI Design Methodology

Volumn 2, Issue , 2009, Pages 167-179

  Zeng, Gang ^a   Tomiyama, Hiroyuki ^a   Takada, Hiroaki ^a  

^a NAGOYA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DEADLINE CONSTRAINT; DYNAMIC ENERGY; DYNAMIC VOLTAGE FREQUENCY SCALING; ENERGY PERFORMANCE TRADEOFFS; ENERGY SAVING; HARD REAL-TIME; HARDWARE CONFIGURATIONS; HARDWARE RESOURCES;

ENERGY CONSERVATION; ENERGY EFFICIENCY; REAL TIME SYSTEMS;

EMBEDDED SYSTEMS;

EID: 79954553620     PISSN: None     EISSN: 18826687     Source Type: Journal    
DOI: 10.2197/ipsjtsldm.2.167     Document Type: Article

References (28)

1. Pillai, P. and Shin, K. G.: Real-Time Dynamic Voltage Scaling for Low-Power Embedded Operating Systems, Proc. ACM Symposium Operating Systems Principles, pp. 89-102 (2001). (Pubitemid 33612607)
2. Kim, W., Shin, D., Yun, H., Kim, J. and Min, S. L.: Performance Comparison of Dynamic Voltage Scaling Algorithms for Hard Real-Time Systems, Proc. IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. 219-228 (2002).
3. Saewong, S. and Rajkumar, R.: Practical Voltage Scaling for Fixed-Priority RT-Systems, Proc. IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. 106-114 (2003).
4. Cho, Y., Chang, N., Chakrabarti, C. and Vrudhula, S.: High-Level Power Management of Embedded Systems with Application-Specific Energy Cost Functions, Proc. Design Automation Conference (DAC), pp. 568-573 (2006). (Pubitemid 47113961)
5. Choi, K., Soma, R. and Pedram, M.: Fine-Grained Dynamic Voltage and Frequency Scaling for Precise Energy and Performance Tradeoff Based on The Ratio of Off-Chip Access to On-Chip Computation Times, IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Vol. 24, No. 1, pp. 18-28 (2005). (Pubitemid 40086145)
6. Shin, D. and Kim, J.: Intra-Task Voltage Scheduling on DVS-Enabled Hard Real-Time Systems, IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Vol. 24, No. 10, pp. 1530-1549 (2005). (Pubitemid 41494283)
7. Yuan, W., Nahrstedt, K., Adve, S. V., Jones, D. L. and Kravets, R. H.: GRACE-1: Cross-Layer Adaptation for Multimedia Quality and Battery Energy, IEEE Trans. Mobile Computing, Vol. 5, No. 7, pp. 799-815 (2006). (Pubitemid 44143931)
8. Albonesi, D. H., Balasubramonian, R., Dropsbo, S. G., et al.: Dynamically Tuning Processor Resources with Adaptive Processing, IEEE Computer, pp. 49-58 (2003).
9. Huang, M., Renau, J. and Torrellas, J.: Positional Adaptation of Processors: Application to Energy Reduction, Proc. IEEE International Symposium Computer Architecture, pp. 157-168 (2003).
10. Chaver, D., Pinuel, L., Prieto, M., Tirado, F. and Huang, M.: Branch Prediction on Demand: An Energy-Efficient Solution, Proc. International Symposium on Low-Power Electronics and Design, pp. 390-395 (2003).
11. Albonesi, D. H.: Selective Cache Ways: on-Demand Cache Resource Allocation, Proc. International Symposium on Microarchitecture (MICRO), pp. 248-259 (1999).
12. Banerjee, S., Surendra, G. and Nandy, S. K.: Program Phase Directed Dynamic Cache Way Reconfiguration for Power Efficiency, Proc. Asia and South Pacific Design Automation Conference (ASPDAC), pp. 884-889 (2007).
13. Buyuktosunoglu, A., et al.: A Circuit-Level Implementation of an Adaptive-Issue Queue for Power-Aware Microprocessors, Proc. Great Lakes Symp. VLSI, pp. 73-78 (2001). (Pubitemid 32456869)
14. Huang, M., Renau, J., Yoo, S. M. and Torrellas, J.: A Framework for Dynamic Energy Efficiency and Temperature Management, Proc. International Symposium on Microarchitecture (MICRO), pp. 202-213 (2000). (Pubitemid 32255843)
15. Nacul, A. and Givargis, T.: Dynamic Voltage and Cache Reconfiguration for Low Power, Proc. Design Automation and Test in Europe (DATE), pp. 1376-1377 (2004).
16. Martello, S. and Toth, P.: Knapsack Problems: Algorithms and Computer Implementations, Wiley (1990).
17. Liu, C. L. and Layland, J. W.: Scheduling Algorithms for Multiprogramming in a Hard Real-Time Environment, Journal of the ACM, Vol. 20, No. 1, pp. 40-61 (1973).
18. Lehoczky, J. P., Sha, L. and Ding, Y.: The Rate Monotonic Scheduling Algorithm: Exact Characterization and Average Case Behavior, Proc. IEEE Real Time Systems Symposium (RTSS), pp. 166-171 (1989). (Pubitemid 20714278)
19. SimpleScalar Tools. http://www.simplescalar.com
20. Sim-Panalyzer Project. http://www.eecs.umich.edu/~panalyzer
21. Guthaus, M. R., Ringenberg, J. S., Ernst, D., Austin, T. M., Mudge, T. and Brown, R. B.: MiBench: A Free, Commercially Representative Embedded Benchmark Suite, IEEE Annual Workshop on Workload Characterization (2001).
22. Lee, C., Potkonjak, M. and Mangione-Smith, W. H.: Mediabench: A Tool for Evaluating and Synthesizing Multimedia and Communications Systems, Proc. International Symposium on Microarchitecture (MICRO), pp. 330-335 (1997).
23. *CORE Architecture, Proc. International. Symposium. on Computer Architecture Power Driven Microarchitecture Workshop, pp. 145-150 (1998).
24. Texas Instruments, Application Report, SPRA848A: Using the Power Scaling Library (2004).
25. Texas Instruments, Application Report, SPRAA19A: Power Management in an RF5 Audio Streaming Application Using DSP/BIOS (2005).
26. Lee, S. and Sakurai, T.: Run-Time Voltage Hopping for Low-Power Real-Time Systems, Proc. Design Automation Conference (DAC), pp. 806-809 (2000).
27. Mochocki, B. C., Hu, X. S. and Quan, G.: A Unified Approach to Variable Voltage Scheduling for Nonideal DVS Processors, IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Vol. 23, No. 9, pp. 1370-1377 (2004).
28. LPSolve tool: http://sourceforge.net/projects/lpsolve