Program phase directed dynamic cache way reconfiguration for power efficiency

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2007, Pages 884-889

  Banerjee, Subhasis ^a   Surendra, G ^b   Nandy, S K ^b  

^a Sun Microsystems   (India)

^b INDIAN INSTITUTE OF SCIENCE   (India)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; DIFFRACTIVE OPTICAL ELEMENTS; DIGITAL INTEGRATED CIRCUITS; DYNAMIC MODELS; INDUSTRIAL ENGINEERING; MECHANIZATION; PIPELINE PROCESSING SYSTEMS; PIPELINES; SULFATE MINERALS;

CACHE UTILIZATION; CRITICAL PATHS; DATA CACHING; DESIGN AUTOMATION CONFERENCE (DAC); DYNAMIC CACHING; DYNAMIC RECONFIGURATIONS; OPTIMAL ALLOCATION; PATH EXECUTION; PHASE INFORMATIONS; POWER BUDGETING; POWER EFFICIENCIES; POWER SAVINGS; PROGRAM BEHAVIORS; PROGRAM PERFORMANCE; PROGRAM PHASES; RUN TIME; SOUTH PACIFIC; SPECULATIVE EXECUTION; SUPERSCALAR PROCESSORS; TOLERABLE LIMIT;

ENERGY CONSERVATION;

EID: 38349068905     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2007.358101     Document Type: Conference Paper

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