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Volumn , Issue , 2003, Pages 390-395

Branch Prediction On Demand: An Energy-Efficient Solution

Author keywords

Adaptive; Branch Prediction; Profiling

Indexed keywords

ADAPTIVE; BRANCH PREDICTION; PROFILING; PARALLEL PROCESSING; PERMISSION; POWER ENGINEERING AND ENERGIES; PREDICTIVE MODELS; RUNTIMES;

EID: 1542359119     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (36)

References (16)
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  • 3
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    • Memory Hierarchy Reconfiguration for Energy and Performance in General-Purpose Processor Architectures
    • Monterey, CA, December
    • R. Balasubramonian, D. Albonesi, A. Buyuktosunoglu, and S. Dwarkadas. Memory Hierarchy Reconfiguration for Energy and Performance in General-Purpose Processor Architectures. In International Symposium on Microarchitecture, pages 245-257, Monterey, CA, December 2000.
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  • 4
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    • Wattch: A Framework for Architectural-Level Power Analysis and Optimizations
    • Göteberg, Sweden, June-July
    • D. Brooks, V. Tiwari, and M. Martonosi. Wattch: A Framework for Architectural-Level Power Analysis and Optimizations. In International Symposium on Computer Architecture, pages 83-94, Göteberg, Sweden, June-July 2001.
    • (2001) International Symposium on Computer Architecture , pp. 83-94
    • Brooks, D.1    Tiwari, V.2    Martonosi, M.3
  • 7
    • 0036398350 scopus 로고    scopus 로고
    • Applying Decay Strategies to Branch Predictors for Leakage Energy Savings
    • Freiburg, Germany, September
    • Z. Hu, P. Juang, K. Skadron, D. Clark, and M. Martonosi. Applying Decay Strategies to Branch Predictors for Leakage Energy Savings. In International Conference on Computer Design, pages 442-445, Freiburg, Germany, September 2002.
    • (2002) International Conference on Computer Design , pp. 442-445
    • Hu, Z.1    Juang, P.2    Skadron, K.3    Clark, D.4    Martonosi, M.5
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    • CACTI: An Enhanced Cache Access and Cycle Time Model
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    • (1996) IEEE Journal of Solid-state Circuits , vol.31 , Issue.5 , pp. 677-688
    • Jouppi, N.1    Wilton, S.2
  • 14
    • 0009554764 scopus 로고    scopus 로고
    • De-aliased Hybrid Branch Predictors
    • Institut National de Recherche en Informatique et en Automatique (INRIA), February
    • A. Seznec and P. Michaud. De-aliased Hybrid Branch Predictors. Technical Report No. 3618, Institut National de Recherche en Informatique et en Automatique (INRIA), February 1999.
    • (1999) Technical Report No. 3618 , vol.3618
    • Seznec, A.1    Michaud, P.2
  • 15
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    • An Integrated Circuit/Architecture Approach to Reducing Leakage in Deep-Submicron High-Performance I-Caches
    • Nuevo Leone, Mexico, January
    • S. Yang, M. Powell, B. Falsafi, K. Roy, and T. Vijaykumar. An Integrated Circuit/Architecture Approach to Reducing Leakage in Deep-Submicron High-Performance I-Caches. In International Symposium on High-Performance Computer Architecture, pages 147-157, Nuevo Leone, Mexico, January 2001.
    • (2001) International Symposium on High-performance Computer Architecture , pp. 147-157
    • Yang, S.1    Powell, M.2    Falsafi, B.3    Roy, K.4    Vijaykumar, T.5
  • 16
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    • The MIPS R10000 Superscalar Microprocessor
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.