53Gbps native GF(24)2 composite-field AES-encrypt/decrypt accelerator for content-protection in 45nm high-performance microprocessors

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2010, Pages 169-170

  Mathew, Sanu ^a   Sheikh, Farhana ^a   Agarwal, Amit ^a   Kounavis, Mike ^a   Hsu, Steven ^a   Kaul, Himanshu ^a   Anders, Mark ^a   Krishnamurthy, Ram ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AREA SAVINGS; DATA PATHS; HARDWARE ACCELERATORS; HIGH-PERFORMANCE MICROPROCESSORS; RE-CONFIGURABLE;

CRYPTOGRAPHY; MICROPROCESSOR CHIPS; RECONFIGURABLE HARDWARE;

VLSI CIRCUITS;

EID: 77958013194     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2010.5560310     Document Type: Conference Paper

References (9)

1. C. Ju et al., ISSCC Dig. of Tech. Papers, pp 152-153, Feb 2009.
2. U. Nawathe et al., ISSCC Dig. of Tech. Papers, pp 108-109, Feb 2007.
3. K. Mistry, et al., IEDM Tech. Dig., pp. 247-250, Dec. 2007.
4. J. Wolkerstorfer, et. al., Crypto. Track at RSA Conf., pp. 67-78, Feb 2002.
5. C. Tokunaga, et al., ISSCC Dig. of Tech. Papers, pp. 64-65, Feb 2009.
6. K. Tiri, et al., VLSI Circuits Symp., Dig of Tech. Papers, pp. 216-219, 2005.
7. S. Morioka, et al., IEEE Trans. on VLSI Sys., pp. 686-691, July 2004.
8. P-C Liu, et al., Proc. of ESSCIRC, pp. 404-407, Sept. 2009
9. N. Pramstaller et al., Proc. of ESSCIRC, pp. 307-310, Sept. 2004