A 10-Gbps full-AES crypto design with a twisted BDD S-box architecture

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 12, Issue 7, 2004, Pages 686-691

  Morioka, Sumio ^a   Satoh, Akashi ^b  

^a SONY CORPORATION   (Japan)

^b IBM RESEARCH   (United States)

Author keywords

Advanced Encryption Standard (AES); ASIC implementation; Binary decision diagram (BDD); Cryptography; High speed hardware; S Box

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; COMBINATORIAL CIRCUITS; COMPUTER HARDWARE; COMPUTER SOFTWARE; CRYPTOGRAPHY; DATA REDUCTION; PIPELINE PROCESSING SYSTEMS; SPECIFICATIONS; STANDARDS;

ADVANCED ENCRYPTION STANDARD (AES); BINARY DECISION DIAGRAM (BDD); HIGH-SPEED HARDWARE; VIRTUAL RPIVATE NETWORK (VPN);

VLSI CIRCUITS;

EID: 3142699811     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2004.830936     Document Type: Conference Paper

References (17)

1. Data Encryption Standard (DES) FIPS Pub 46-3 (1999, Oct.). [Online]. Available: http://csrc.nist.gov/publications/fips/fips46-3/fips46-3.pdf
2. J. Daemen and V. Rijmen, The Design of Rijndael. New York: Springer-Verlag, 2002.
3. Advanced Encryption Standard (AES) PIPS Pub 197 (2001, Nov.). [Online]. Available: http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf
4. T. Ichikawa, T. Kasuya, and M. Matsui, "Hardware evaluation of the AES finalists," in Proc. 3rd AES Candidate Conf., 2000, pp. 279-285.
5. H. Kuo and I. Verbauwhede, "Architectural optimization for a 1.82 Gbps VLSI implementation of the AES Rijndael algorithm," in Proc. CHES, vol. 2162, 2001, pp. 53-67.
6. I. Verbauwhede, P. Schaumont, and H. Kuo, "Design and performance testing of a 2.29-GB/s Rijndael processor," IEEE J. Solid-State Circuits, vol. 38, pp. 569-572, Mar. 2001.
7. B. Weeks, M. Bean, T. Rozylowicz, and C. Ficke. (1999, Oct.) Hardware performance simulation of round 2 advanced encryption standard algorithm. [Online]. Available: http://csrc.nist.gov/encryption/aes/round2/NSA- AESfinalreport.pdf
8. M. McLoone and J. McCanny, "High performance single-chip FPOA Rijndael algorithm implementations," in Proc. CHES, 2001, pp. 68-80.
9. V. Fischer and M. Drutarovský, "Two methods of Rijndael implementation in reconfigurable hardware," in Proc. CHES, vol. 2162, 2001, pp. 81-96.
10. J. Guajardo and C. Paar, "Efficient algorithms for elliptic curve cryptosystems," in Proc. 17th Annual Int. Cryptology Conf. (CRYPTO'97), vol. 1294, 1997, pp. 342-356.
11. A. Rudra, P. K. Dubey, C. S. Jutla, V. Kumar, J. R. Rao, and P. Rohatgi, "Efficient Rijndael encryption implementation with composite field arithmetic," in Proc. CHES, vol. 2162, 2001, pp. 175-188.
12. A. Satoh, S. Morioka, K. Takano, and S. Munetoh, "A compact Rijndael hardware architecture with S-Box optimization," in Proc. Asia Crypt, vol. 2248, 2001, pp. 239-254.
13. U. Mayer, C. Oelsner, and T. Kohler, "Evaluation of different Rijndael implementations for high-end servers," in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), 2002.
14. R. E. Bryant, "Graph-Based algorithms for Boolean function manipulation," IEEE Trans. Computers, vol. C-35, pp. 677-691, Aug. 1986.
15. T. Sasao, "AND-EXOR expressions and their optimization," in Logic Synthesis and Optimization, Sasao, Ed. Norwell, MA: Kluwer, 1993.
16. U. Kebshull and W. Rosenstiel, "Efficient graph-based computation and manipulation of functional decision diagrams," in Proc. Eur. Design Automation Conf., 1993, pp. 278-282.
17. m)," in Proc. 13th Conf. Computer-Aided Verification (CAV), vol. 2102, LNCS, 2001, pp. 465-477.