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Volumn 2005, Issue , 2005, Pages 216-219

AES-based cryptographic and biometric security coprocessor IC in 0.18-μ;m CMOS resistant to side-channel power analysis attacks

Author keywords

Advanced Encryption Standard (AES); Biometrics; Coprocessor; Cryptography; Differential power analysis

Indexed keywords

ADVANCED ENCRYPTION STANDARD (AES); BIOMETRICS; COPROCESSOR; DIFFERENTIAL POWER ANALYSIS;

EID: 33645692468     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2005.1469370     Document Type: Conference Paper
Times cited : (27)

References (9)
  • 2
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    • Security as a new dimension in embedded system design
    • P. Kocher, R. Lee, G. McGraw, A. Raghunathan and S. Ravi, "Security as a New Dimension in Embedded System Design," DAC, pp. 753-760, 2004.
    • (2004) DAC , pp. 753-760
    • Kocher, P.1    Lee, R.2    McGraw, G.3    Raghunathan, A.4    Ravi, S.5
  • 3
    • 27944445926 scopus 로고    scopus 로고
    • A hardware DES cracker
    • August
    • B. Schneier, "A Hardware DES Cracker," Crypto-Gram Newsletter, http://www.schneier.com/crypto-gram-9808.htm#descracker, August 1998.
    • (1998) Crypto-gram Newsletter
    • Schneier, B.1
  • 4
    • 3042604811 scopus 로고    scopus 로고
    • A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation
    • K. Tin and I. Verbauwhede, "A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation," DATE, pp. 246-251, 2004.
    • (2004) DATE , pp. 246-251
    • Tin, K.1    Verbauwhede, I.2
  • 5
    • 33645696140 scopus 로고    scopus 로고
    • International Technology Roadmap for Semiconductors
    • ITRS, "Interconnect," International Technology Roadmap for Semiconductors, http://public.itrs.net/Files/2003ITRS/Interconnect2003.pdf, 2003.
    • (2003) Interconnect
  • 6
    • 84902478964 scopus 로고    scopus 로고
    • Place and route for secure standard cell design
    • K. Tiri and I. Verbauwhede, "Place and Route for Secure Standard Cell Design," CARDIS, pp. 143-158, 2004.
    • (2004) CARDIS , pp. 143-158
    • Tiri, K.1    Verbauwhede, I.2
  • 8
    • 35248826454 scopus 로고    scopus 로고
    • Security evaluation of asynchronous circuits
    • J. Fournier, S. Moore, H. Li, R. Mullins and G. Taylor, "Security Evaluation of Asynchronous Circuits," CHES, pp. 137-151, 2003.
    • (2003) CHES , pp. 137-151
    • Fournier, J.1    Moore, S.2    Li, H.3    Mullins, R.4    Taylor, G.5


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.