A 500-MHz multi-banked compilable DRAM macro with direct write and programmable pipelining

IEEE Journal of Solid-State Circuits

Volumn 40, Issue 1, 2005, Pages 213-221

  Barth Jr , John E ^a   Anand, Darren ^a   Burns, Steve ^a   Dreibelbis, Jeffrey H ^a   Fifield, John A ^a   Gorman, Kevin ^a   Nelms, Michael ^a   Nelson, Erik ^a   Paparelli, Adrian ^b   Pomichter, Gary ^a   Pontius, Dale E ^a   Sliva, Stephen ^a  

^a IBM   (United States)

^b IBM MICROELECTRONICS   (United States)

Author keywords

DRAM macro

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; BANDWIDTH; ELECTRIC FUSES; LOGIC DESIGN; LOGIC DEVICES; OPTIMIZATION; STATIC RANDOM ACCESS STORAGE; TOPOLOGY;

BUILT-IN SELF-TEST (BIST) CIRCUITS; DRAM MACRO; GROUND SENSING; PROGRAMMABLE PIPELINING;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 19944427208     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2004.838001     Document Type: Conference Paper

References (5)

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3. H. Pilo et al., "A 5.6 ns random cycle 144 Mb DRAM with 1.4 Gb/s/pin and DDR3-SRAM interface," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, vol. XLVI, Feb. 2003, pp. 308-309.
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