A 45nm SOI embedded DRAM macro for POWER7™ 32MB on-chip L3 cache

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 53, Issue , 2010, Pages 342-343

  Barth, John ^a   Plass, Don ^a   Nelson, Erik ^a   Hwang, Charlie ^a   Fredeman, Gregory ^a   Sperling, Michael ^a   Mathews, Abraham ^a   Reohr, William ^b   Nair, Kavita ^a   Cao, Nianzheng ^a  

^a IBM   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ASIC APPLICATION; DEEP TRENCH; DRAM DEVICES; DRAM MACRO; EMBEDDED DRAM; HIGH-PERFORMANCE MICROPROCESSORS; IMPROVING SYSTEMS; LOGIC TECHNOLOGY; OFF-CHIP; OFF-CHIP INTERFACES; ON CHIPS; PLANAR STRUCTURE; REDUCING COSTS; SEM; SENSE AMP; SOFT ERROR; SUPPLY NOISE; VOLTAGE ISLAND;

CAPACITANCE; COST REDUCTION; SUPERCOMPUTERS;

MICROPROCESSOR CHIPS;

EID: 77952114330     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2010.5433814     Document Type: Conference Paper

References (7)

1. H. Pilo, et al, "A 5.6-ns Random Cycle 144-Mb DRAM with 1.4Gb/s/pin and DDR3-RAM Interface", JSSC, Nov. 2003,.
2. J. Friedrich, et al, "POWER6™", ISSCC 2007.
3. S. Iyer, et al., "Embedded DRAM: Technology Platform for Blue Gene/L Chip", IBM J. Res.Dev., Mar./May, 2005.
4. P.Klim, et el, "One MB cache Subsystem Prototype", VLSI Circuits Symposium 2008.
5. B. Starke, et al, "POWER7™", Hot Chips 2009.
6. J. Barth, et al, "A 500MHz Random Cycle 1.5ns, SOI Embedded DRAM Macro", ISSCC 2007.
7. G.Wang, et al, "Scaling Deep Trench Based eDRAM on SOI to 32nm and Beyond", IEDM 2008.