A chip-stacked memory for on-chip SRAM-rich SoCs and processors

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2009, Pages

  Saito, Hideaki ^a   Nakajima, Masayuki ^a   Okamoto, Takumi ^a   Yamada, Yusuke ^a   Ohuchi, Akira ^a   Iguchi, Noriyuki ^a   Sakamoto, Toshitsugu ^a   Yamaguchi, Koichi ^a   Mizuno, Masayuki ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 70349280619     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2009.4977307     Document Type: Conference Paper

References (5)

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3. S. Kunie, T. Hiraga, T. Tokue, et al., "Low Power Architecture and Design Techniques for Mobile Handset LSI MedityTM M2," Proceeding of ASPDAC, pp. 748-753, 2008.
4. T. Ezaki, K. Kondo, H. Ozaki, et al., "A 160Gb/s Interface Design Configuration for Multichip LSI," ISSCC Dig. Tech. Papers, pp. 140-141, 2004.
5. K. Kumagai, C. Yang, H. Izumino, et al., "System-in-Silicon Architecture and its Application to H.264/AVC Motion Estimation for 1080HDTV," ISSCC Dig. Tech. Papers, pp. 1706-1707, 2006.