Single-crystalline Si STacked ARray (STAR) NAND flash memory

IEEE Transactions on Electron Devices

Volumn 58, Issue 4, 2011, Pages 1006-1014

  Yun, Jang Gn ^a   Kim, Garam ^b   Lee, Joung Eob ^b   Kim, Yoon ^b   Shim, Won Bo ^b   Lee, Jong Ho ^b   Shin, Hyungcheol ^b   Lee, Jong Duk ^b   Park, Byung Gook ^b  

^a SAMSUNG Electronics   (South Korea)

^b Seoul National University   (South Korea)

Author keywords

Damascene gate process; layer replacement and single crystal Si nanowire; nand Flash memory; stacked bit lines; three dimensional (3 D) memory

Indexed keywords

DAMASCENE GATE PROCESS; LAYER REPLACEMENT AND SINGLE-CRYSTAL SI NANOWIRE; NAND FLASH MEMORY; STACKED BIT LINES; THREE-DIMENSIONAL (3-D) MEMORY;

ELECTRIC WIRE; NAND CIRCUITS; NANOWIRES; SILICON; THREE DIMENSIONAL;

FLASH MEMORY;

EID: 79953086976     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2011.2107557     Document Type: Article

References (21)

1. S. Lai, "Non-volatile memory technologies: The quest for ever lower cost," in IEDM Tech. Dig., 2008, pp. 11-16.
2. K. Kim and D. Park, "The future outlook of memory devices," in Proc. 37th Eur. Solid State Device Res. Conf., 2007, p. 47. (Pubitemid 351278179)
3. A. Fazio, "Future directions of non-volatile memory in compute applications," in IEDM Tech. Dig., 2009, pp. 641-644.
4. H. Tanaka, M. Kido, K. Yahashi, M. Oomura, R. Katsumata, M. Kito, Y. Fukuzumi, M. Sato, Y. Nagata, Y. Matsuoka, Y. Iwata, H. Aochi, and A. Nitayama, "Bit cost scalable technology with punch and plug process for ultra high density flash memory," in VLSI Symp. Tech. Dig., 2007, pp. 14-15.
5. Y. Fukuzumi, R. Katsumata, M. Kito, M. Kido, M. Sato, H. Tanaka, Y. Nagata, Y. Matsuoka, Y. Iwata, H. Aochi, and A. Nitayama, "Optimal integration and characteristics of vertical device for ultra-high density, bit-cost scalable flash memory," in IEDM Tech. Dig., 2007, pp. 449-452.
6. J. Kim, A. J. Hong, M. Ogawa, S. Ma, E. B. Song, Y. S. Lin, J. Han, U. I. Chung, and K. L. Wang, "Novel 3-D structure for ultra high density flash memory with VRAT (vertical-recess-array-transistor) and PIPE (planarized integration on the same PlanE)," in VLSI Symp. Tech. Dig., 2008, pp. 122-123.
7. J. Jang, H. S. Kim, W. Cho, H. Cho, J. Kim, S. I. Shim, Y. Jang, J. H. Jeong, B. K. Son, D. W. Kim, K. Kim, J. J. Shim, J. S. Lim, K. H. Kim, S. Y. Yi, J. Y. Lim, D. Chung, H. C. Moon, S. Hwang, J.W. Lee, Y. H. Son, U. I. Chung, andW. S. Lee, "Vertical cell array using TCAT (Terabit Cell Array Transistor) technology for ultra high density NAND flash memory," in VLSI Symp. Tech. Dig., 2008, pp. 192-193.
8. Y. Komori, M. Kido, M. Kito, R. Katsumata, Y. Fukuzumi, H. Tanaka, Y. Nagata, M. Ishiduki, H. Aochi, and A. Nitayama, "Disturbless flash memory due to high boost efficiency on BiCS structure and optimal memory film stack for ultra high density storage device," in IEDM Tech. Dig., 2008, pp. 851-854.
9. R. Katsumata, M. Kito, Y. Fukuzumi, M. Kido, H. Tanaka, Y. Komori, M. Ishiduki, J. Matsunami, T. Fujiwara, Y. Nagata, L. Zhang, Y. Iwata, R. Kirisawa, H. Aochi, and A. Nitayama, "Pipe-shaped BiCS flash memory with 16 stacked layers and multi-level-cell operation for ultra high density storage devices," in VLSI Symp. Tech. Dig., 2009, pp. 136-137.
10. J. Kim, A. J. Hong, S. M. Kim, E. B. Song, J. H. Park, J. Han, S. Choi, D. Jang, J. T. Moon, and K. L. Wang, "Novel vertical-stacked- arraytransistor (VSAT) for ultra-high-density and cost-effective NAND Flash memory devices and SSD (Solid State Drive)," in VLSI Symp. Tech. Dig., 2009, pp. 186-187.
11. W. Kim, S. Choi, J. Sung, T. Lee, C. Park, H. Ko, J. Jung, I. Yoo, and Y. Park, "Multi-layered vertical gate NAND flash overcoming stacking limit for terabit density storage," in VLSI Symp. Tech. Dig., 2009, pp. 188-189.
12. A. Hubert, E. Nowak, K. Tachi, V. Maffini-Alvaro, C. Vizioz, C. Arvet, J.-P. Colonna, J.-M. Hartmann, V. Loup, L. Baud, S. Pauliac, V. Delaye, C. Carabasse, G. Molas, G. Ghibaudo, B. De Salvo, O. Faynot, and T. Ernst, "A stacked SONOS technology, up to 4 levels and 6nm crystalline nanowires, with gate-all-around or independent gates ( F-Flash), suitable for full 3D integration," in IEDM Tech. Dig., 2009, pp. 637-640.
13. K. T. Park, M. Kang, S. Hwang, D. Kim, H. Cho, Y. Jeong, Y. I. Seo, J. Jang, H. S. Kim, Y. T. Lee, S. M. Jung, and C. Kim, "A fully performance compatible 45 nm 4-Gigabit three dimensional double-stacked multi-level NAND flash memory with shared bit-line structure," IEEE J. Solid-State Circuits, vol. 44, no. 1, pp. 208-216, Jan. 2009.
14. S. M. Jung, J. Jang,W. Cho, H. J. Cho, J. Jeong, Y. Chang, J. Kim, Y. Rah, Y. Son, J. Park, M. S. Song, K. H. Kim, J. S. Lim, and K. Kim, "Three dimensionally stacked NAND flash memory technology using stacking single crystal Si layers on ILD and TANOS structure for beyond 30 nm node," in IEDM Tech. Dig., 2006, pp. 1-4.
15. E. K. Lai, H. T. Lue, Y. H. Hsiao, J. Y. Hsieh, S. C. Lee, C. P. Lu, S. Y. Wang, L. W. Yang, K. C. Chen, J. Gong, K. Y. Hsieh, J. R. Liu, and C. Y. Lu, "A highly stackable thin-film transistor (TFT) NAND-type flash memory," in VLSI Symp. Tech. Dig., 2006, pp. 46-47. (Pubitemid 351424118)
16. H. T. Lue, T. H. Hsu, Y. H. Hsiao, S. P. Hong, M. T. Wu, F. H. Hsu, N. Z. Lien, S. Y. Wang, J. Y. Hsieh, L. W. Yang, T. Yang, K. C. Chen, K. Y. Hsieh, and C. Y. Lu, "A highly scalable 8-layer 3D vertical-gate (VG) TFT NAND flash using junction-free buried channel BE-SONOS device," in VLSI Symp. Tech. Dig., 2010, pp. 131-132.
17. K. H. Yeo, K. H. Cho, M. Li, S. D. Suk, Y. Yeoh, M. S. Kim, H. Bae, J. M. Lee, S. K. Sung, J. Seo, B. Park, D. W. Kim, D. Park, and W. S. Lee, "Gate-all-round single silicon nanowire MOSFET with 7 nm width for SONOS NAND flash memory," in VLSI Symp. Tech. Dig., 2008, pp. 138-139.
18. J. H. Lee, I. H. Park, S. Cho, G. S. Lee, D. H. Kim, J. G. Yun, Y. Kim, J. D. Lee, and B. G. Park, "Enhanced program/erase characteristic of arch shaped SONOS flash memory," in Proc. 9th Int. Conf. Electron., Inf., Commun., 2008, pp. 1029-1032.
19. T. H. Hsu, H. T. Lue, E. K. Lai, J. Y. Heieh, S. Y. Wang, L. W. Yang, Y. C. King, T. Yang, K. C. Chen, K. Y. Hsieh, R. Liu, and C. Y. Lu, "A high-speed BE-SONOS NAND flash utilizing the field-enhancement effect of FinFET," in IEDM Tech. Dig., 2007, pp. 913-916.
20. A. J. Walker, "Sub-50nm DG-TFT-SONOS-The ideal flash memory for monolithic 3-D integration," in IEDM Tech. Dig., 2008, pp. 1-4.
21. A. J. Walker, "Sub-50-nm dual-gate thin-film transistors for monolithic 3-D flash," IEEE Trans. Electron Devices, vol. 56, no. 11, pp. 2703-2710, Nov. 2009.