High mobility CMOS: First demonstration of planar GeOI p-FETs with SOI n-FETs

Solid-State Electronics

Volumn 59, Issue 1, 2011, Pages 2-7

  Le Royer, C ^a   Damlencourt, J F ^a   Vincent, B ^a   Romanjek, K ^a   Le Cunff, Y ^a   Grampeix, H ^a   Mazzocchi, V ^a   Carron, V ^a   Nemouchi F ^a   Hartmann, J M ^a   Arvet, C ^a   Vizioz, C ^a   Tabone, C ^a   Hutin, L ^a   Batude, P ^a   Vinet, M ^a  

^a CEA LETI   (France)

Author keywords

CMOS; Ge enrichment technique; GeOI; Germanium; High mobility; Silicium; SOI

Indexed keywords

CMOS; ENRICHMENT TECHNIQUES; GEOI; HIGH MOBILITY; SILICIUM; SOI;

MESFET DEVICES; SEMICONDUCTING SILICON COMPOUNDS; SILICON; SILICON WAFERS;

GERMANIUM;

EID: 79953045169     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2011.01.012     Document Type: Conference Paper

References (19)

1. J. Feng, Y. Liu, P.B. Griffin, and J.D. Plummer Integration of germanium-on-insulator and silicon MOSFETs on a silicon substrate IEEE Electron Dev Lett 27 11 2006 911 913 (Pubitemid 44660650)
2. Mitard J et al. Impact of EOT scaling down to 0.85 nm on 70 nm Ge-pFETs technology with STI. In: Proc VLSI Tech. Symp; 2009. p. 82-3.
3. K. Romanjek, L. Hutin, C. Le Royer, A. Pouydebasque, M.-A. Jaud, and C. Tabone High performance 70 nm gate length germanium-on-insulator pMOSFET with high-k/metal gate Solid-State Electron 53 2009 723 729
4. A. Pouydebasque, K. Romanjek, C. Le Royer, C. Tabone, B. Previtali, and F. Allain Experimental evidence of sidewall enhanced transport properties of mesa-isolated (0 0 1) germanium-on-insulator pMOSFETs IEEE Trans Electron Dev 56 12 2009 3240 3244
5. L. Hutin, C. Le Royer, J.-F. Damlencourt, J.-M. Hartmann, H. Grampeix, and V. Mazzocchi GeOI pMOSFETs scaled down to 30 nm gate length with record off-state current IEEE Electron Dev Lett 31 3 2010 234 236
6. Nguyen QT, Damlencourt J-F, Vincent B, Loup V, Le Cunff Y, Gentil P, et al. SOI-GeOI hybrid substrates elaboration by ge condensation: process and electrical properties. In: Proc SOI conference; 2008. p. 103-4.
7. S. Takagi Device structures and carrier transport properties of advanced CMOS using high mobility channels Solid-State Electron 51 2007 526 536 (Pubitemid 46550573)
8. Lee CH, Nishimura T, Saido N, Nagashio K, Kita K, Toriumi A. Record-high electron mobility in Ge n-MOSFETs exceeding Si Universality. In: Proc IEDM; 2009. p. 457-60.
9. Batude P, Vinet M, Pouydebasque A, Le Royer C, Previtali B, Tabone C, et al. GeOI and SOI 3D monolithic cell integrations for high density applications. In: Proc VLSI technol symp; 2009. p. 166-7.
10. Nemouchi F, Carron V, Morand Y, Descombes S, Pedini J-M, Le Royer C, et al. Nickel metallization process for low resistance contact formation on planar co-integration nMOS-Si and pMOS-Ge on Insulator. In: MRS spring; 2008 [abstract E2.4].
11. Damlencourt J-F, Vincent B, Rivallin P, Holliger P, Rouchon D, Nolot E, et al. Fabrication of SiGe-on-insulator by improved ge condensation technique. In: Proc ISTDM; 2006. p. 202-8.
12. B. Vincent, J.-F. Damlencourt, Y. Morand, A. Pouydebasque, C. Le Royer, and L. Clavelier The Ge condensation technique: a solution for planar SOI/GeOI co-integration for advanced CMOS technologies? Mater Sci Semicond Process 11 2008 205 213
13. J.-M. Hartmann, A. Abbadie, N. Cherkashin, H. Grampeix, and L. Clavelier Epitaxial growth of Ge thick layers on nominal and 6° off Si(0 0 1); Ge surface passivation by Si Semicond Sci Technol 24 2009 055002
14. S. Gaudet, C. Detavernier, A.J. Kellock, P. Desjardins, and C. Lavoie J Vac Sci Technol A24 2006 474
15. Carron V, Rolland G, Minoret S, Hartmann JM, Clavelier L, Le Royer C. Nickel selective etching studies for self-aligned silicide process in Ge-based devices. In: ECS 210th meeting [abstract 1467].
16. 3 and NiGe by reaction of Ni film with Ge Appl Phys Lett 89 2006 131920
17. W. Van Den Daele, E. Augendre, K. Romanjek, C. Le Royer, L. Clavelier, and J.-F. Damlencourt Low-temperature measurements on germanium-on-insulator pMOSFETs: evaluation of the background doping level and modeling of the threshold voltage temperature dependence ECS Trans 19 4 2009 145 152 [device physics and modeling II]
18. Weber O, Faynot O, Andrieu F, Buj-Dufournet C, Allain F, Scheiblin P, et al. High immunity to threshold voltage variability in undoped ultra-thin FDSOI MOSFETs and its physical understanding. In: Proc international electron devices meeting; 2008. p. 245-8 [IEDM 2008].
19. G. Ghibaudo New method for the extraction of MOSFET parameters Electron Lett 24 9 1988 543