GeOI and SOI 3D monolithic cell integrations for high density applications

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2009, Pages 166-167

  Batude, P ^a   Vinet, M ^a   Pouydebasque, A ^a   Le Royer, C ^a   Previtali, B ^a   Tabone, C ^a   Clavelier, L ^a   Michaud, S ^a   Valentian, A ^a   Thomas, O ^a   Rozeau, O ^a   Coudrain, P ^b   Leyris, C ^b   Romanjek, K ^a   Garros, X ^a   Sanchez, L ^a   Baud, L ^a   Roman, A ^a   Canon, V ^a   Grampeix, H ^a   Augendre, B ^a   Toffoli, A ^a   Allain, F ^a   Grosgeorges, P ^a   Mazzochi, V ^a   Tosti, L ^a   Andrieu, F ^a   Hartmann, J M ^a   Lafond, D ^a   Deleonibus, S ^a   Faynot, O ^a   more..

^a CEA LETI   (France)

^b STMICROELECTRONICS   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ACTIVE LAYER; ADVANCED DESIGNS; HIGH-DENSITY APPLICATIONS; LOW-TEMPERATURE PROCESS; MONOLITHIC CELL INTEGRATION; PROCESS TEMPERATURE; SHORT-CHANNEL EFFECT; SOI-MOSFETS;

DESIGN; THREE DIMENSIONAL; WAFER BONDING;

SILICON WAFERS;

EID: 71049124419     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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