Enhancement-mode InAlN/AlN/GaN HEMTs with 10-12A/mm leakage current and 10-12 on/off current ratio

IEEE Electron Device Letters

Volumn 32, Issue 3, 2011, Pages 309-311

  Wang, Ronghua ^a   Saunier, Paul ^b   Tang, Yong ^a   Fang, Tian ^a   Gao, Xiang ^c   Guo, Shiping ^c   Snider, Gregory ^a   Fay, Patrick ^a   Jena, Debdeep ^a   Xing, Huili ^a  

^a University of Notre Dame   (United States)

^b TRIQUINT SEMICONDUCTOR   (United States)

^c IQE INC   (United States)

Author keywords

Enhancement mode (E mode); gate leakage current; InAlN; postprocessing annealing

Indexed keywords

BARRIER HEIGHTS; BREAKDOWN VOLTAGE; ENHANCEMENT MODES; ENHANCEMENT-MODE; FORMING GAS; GATE DIODES; GATE RECESS PROCESS; GATE-LEAKAGE CURRENT; INALN; INTERFACE STATE; LATTICE-MATCHED; OFF CURRENT; ON/OFF CURRENT RATIO; POSTPROCESSING ANNEALING; REVERSE GATE; SELECTIVE ETCH; THIN OXIDE LAYERS;

ANNEALING; GALLIUM ALLOYS; GALLIUM NITRIDE; LEAKAGE CURRENTS; PLATINUM;

HIGH ELECTRON MOBILITY TRANSISTORS;

EID: 79951954254     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2010.2095494     Document Type: Article

References (16)

1. H. Wang, J. W. Chung, X. Gao, S. Guo, and T. Palacios, "High performance InAlN/GaN HEMTs on SiC substrate," in Proc. CS MANTECH Conf. Dig., 2010, pp. 185-188.
2. F. Medjdoub, J.-F. Carlin, M. Gonschorek, E. Feltin, M. A. Py, D. Ducatteau, C. Gaquiere, N. Grandjean, E. Kohn, "Can InAlN/GaN be an alternative to high power/high temperature AlGaN/GaN devices?" in IEDM Tech. Dig., 2006, pp. 1-4.
3. H. Sun, A. R. Alt, H. Benedickter, E. Feltin, J.-F. Carlin, M. Gonschorek, N. R. Grandjean, and C. R. Bolognesi, "205-GHz (Al, In)N/GaN HEMTs," IEEE Electron Device Lett., vol. 31, no. 9, pp. 957-959, Sep. 2010.
4. C. Sanabria, A. Chakraborty, H. Xu, M. J. Rodwell, U. K. Mishra, and R. A. York, "The effect of gate leakage on the noise figure of AlGaN/GaN HEMTs," IEEE Electron Device Lett., vol. 27, no. 1, pp. 19-21, Jan. 2006.
5. W. Saito, M. Kuraguchi, Y. Takada, K. Tsuda, I. Omura, and T. Ogura, "High breakdown voltage undoped AlGaN-GaN power HEMT on sapphire substrate and its demonstration for DC-DC converter application," IEEE Trans. Electron Devices, vol. 51, no. 11, pp. 1913-1917, Nov. 2004.
6. V. Adivarahan, J. Yang, A. Koudymov, G. Simin, and M. A. Khan, "Stable CW operation of field-plated GaN-AlGaN MOSHFETs at 19 W/mm," IEEE Electron Device Lett., vol. 26, no. 8, pp. 535-537, Aug. 2005. (Pubitemid 41179166)
7. J. W. Chung, J. C. Roberts, E. L. Piner, and T. Palacios, "Effect of gate leakage in the subthreshold characteristics of AlGaN/GaN HEMTs," IEEE Electron Device Lett., vol. 29, no. 11, pp. 1196-1198, Nov. 2008.
8. R. Chu, L. Shen, N. Fichtenbaum, D. Brown, S. Keller, and U. K. Mishra, "Plasma treatment for leakage reduction in AlGaN/GaN and GaN Schottky contacts," IEEE Electron Device Lett., vol. 29, no. 4, pp. 297-299, Apr. 2008. (Pubitemid 351486763)
9. Y. Lin, Y. Lain, and S. S. H. Hsu, "AlGaN/GaN HEMTs with low leakage current and high ON/OFF current ratio," IEEE Electron Device Lett., vol. 31, no. 2, pp. 102-104, Feb. 2010.
10. R. Wang, P. Sanier, X. Xing, C. Lian, X. Gao, S. Guo, G. Snider, P. Fay, D. Jena, and H. Xing, "Gate-recessed enhancement-mode InAlN/AlN/GaN HEMTs with 1.9 A/mm drain current density and 800 mS/mm transconductance," IEEE Electron Device Lett., vol. 31, no. 12, pp. 1383-1385, Dec. 2010.
11. K. J. Chen, T. Enoki, K. Maezawa, K. Arai, and M. Yamamoto, "High performance InP-based enhancement-mode HEMTs using non-alloyed ohmic contacts and Pt-based buried-gate technologies," IEEE Trans. Electron Devices, vol. 43, no. 2, pp. 252-257, Feb. 1996. (Pubitemid 126768114)
12. C. Ostermaier, G. Pozzovivo, B. Basnar, W. Schrenk, M. Schmid, L. Tóth, B. Pécz, J.-F. Carlin, M. Gonschorek, N. Grandjean, G. Strasser, D. Pogany, and J. Kuzmik, "Metal-related gate sinking due to interfacial oxygen layer in Ir/InAlN high electron mobility transistors," Appl. Phys. Lett., vol. 96, no. 26, p. 263 515, Jul. 2010.
13. A. Fricke, G. Stareev, T. Kummetz, D. Sowada, J. Mahnss, W. Kowalsky, and K. J. Ebeling, "1.09-eV Schottky barrier height of nearly ideal Pt/Au contacts directly deposited on n-and p+n-A10.48In0.52As layers," Appl. Phys. Lett., vol. 65, no. 6, pp. 755-757, Aug. 1994.
14. S. Singhal, J. C. Roberts, P. Rajagopal, T. Li, A. W. Hanson, R. Therrien, J. W. Johnson, I. C. Kizilyalli, and K. J. Linthicum, "GaN-on-Si failure mechanisms and reliability improvements," in Proc. IRPS, 2006, pp. 95-98. (Pubitemid 46964496)
15. P. Rottlander, M. Hehn, and A. Schuhl, "Determining the interfacial barrier height and its relation to tunnel magnetoresistance," Phys. Rev. B, Condens. Matter, vol. 65, no. 5, p. 054 422, Jan. 2002.
16. K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, "Leakage current mechanisms and leakage reduction techniques in deepsubmicrometer CMOS circuits," Proc. IEEE, vol. 91, no. 2, pp. 305-327, Feb. 2003. (Pubitemid 43779250)