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Volumn , Issue , 2010, Pages 321-324

Reliability approach of high density Through Silicon Via (TSV)

Author keywords

Electromigration; Failure criterion; Reliability; Thermal cycling; Through Silicon Via (TSV); Void

Indexed keywords

A-CARBON; ELECTRICAL RESISTANCES; FAILURE CRITERIA; FAILURE CRITERION; HIGH DENSITY; PHYSICAL ANALYSIS; RELIABILITY APPROACH; THERMAL CYCLING TEST; THROUGH-SILICON-VIA; TIME TO FAILURE; VOID;

EID: 79951904993     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPTC.2010.5702655     Document Type: Conference Paper
Times cited : (37)

References (13)
  • 1
    • 70449088867 scopus 로고    scopus 로고
    • Performance and Reliability Analysis of 3D-Itegration Structures Employing Through Silicon Via (TSV)
    • th, 2009, pp. 682-687.
    • th, 2009 , pp. 682-687
    • Karmarkar, A.P.1
  • 2
    • 70349675218 scopus 로고    scopus 로고
    • Failure Mechanisms and Optimum Desing for Electroplated Copper Through-Silicon Vias (TSV)
    • th, 2009, pp. 624-629.
    • th, 2009 , pp. 624-629
    • Liu, X.1
  • 3
    • 70349670752 scopus 로고    scopus 로고
    • Thermo-Mechanical Reliability of 3-D ICs containing Through Silicon Vias
    • th, 2009, pp. 630-634.
    • th, 2009 , pp. 630-634
    • Lu, K.H.1
  • 5
    • 34748889075 scopus 로고    scopus 로고
    • Challenges for 3D IC integration: Bonding quality and thermal management
    • P. Leduc, et al., "Challenges for 3D IC integration: bonding quality and thermal management", International Interconnect Technology Conference, 2007, pp. 210-212.
    • International Interconnect Technology Conference, 2007 , pp. 210-212
    • Leduc, P.1
  • 6
    • 0003950677 scopus 로고    scopus 로고
    • Method of anisotropically etching silicon
    • U.S. Patent No. 5501893 (March 26)
    • F. Laermer, et al., "Method of anisotropically etching silicon", U.S. Patent No. 5501893 (March 26, 1996).
    • (1996)
    • Laermer, F.1
  • 9
    • 77952402732 scopus 로고    scopus 로고
    • Enabling 3D-IC foundry technologies for 28nm node and beyond: Through-silicon-via integration with high throughput die-to-wafer stacking
    • D.Y. Chen, et al., "Enabling 3D-IC foundry technologies for 28nm node and beyond: through-silicon-via integration with high throughput die-to-wafer stacking", International Electron Devices Meeting, 2009, pp. 1-4.
    • International Electron Devices Meeting, 2009 , pp. 1-4
    • Chen, D.Y.1
  • 10
    • 51349132537 scopus 로고    scopus 로고
    • Through silicon via technology - Processes and reliability for wafer-level 3D system integration
    • th, 2008, pp. 841-846.
    • th, 2008 , pp. 841-846
    • Ramm, P.1
  • 13
    • 0036892397 scopus 로고    scopus 로고
    • Electromigration reliability issues in dual-damascene Cu interconnections
    • E. T. Ogawa, et al., " Electromigration reliability issues in dual-damascene Cu interconnections", Transactions on Reliability, 2002, Vol. 51, Iss. 4, pp. 403-419.
    • (2002) Transactions on Reliability , vol.51 , Issue.4 , pp. 403-419
    • Ogawa, E.T.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.