Test structures for characterization of through silicon vias

IEEE International Conference on Microelectronic Test Structures

Volumn , Issue , 2010, Pages 130-134

  Stucchi, M ^a   Perry, D ^b   Katti, G ^c   Dehaene, W ^c  

^a IMEC   (Belgium)

^b QUALCOMM INC   (United States)

^c UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

3D stack; Capacitance; Electrical measurements; Leakage; RO (ring oscillator); SPICE simulations; TSV (through silicon via); TSV resistance; Yield

Indexed keywords

ELECTRICAL MEASUREMENT; RING OSCILLATOR; RO (RING OSCILLATOR); SPICE SIMULATIONS; THROUGH-SILICON-VIA;

CAPACITANCE; ELECTRIC VARIABLES MEASUREMENT; MICROELECTRONICS; THREE DIMENSIONAL;

OSCILLATORS (ELECTRONIC);

EID: 77953890608     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICMTS.2010.5466841     Document Type: Conference Paper

References (4)

1. Jan Van Olmen et al., "3D Stacked IC Demonstration using a Trough Silicon Via First Approach", Technical Digest of the International Electron Device Meeting 2008, pp. 603-616.
2. G. Katti et al., "3D Stacked ICs using Cu TSVs and Die to Wafer Hybrid Collective Bonding", Technical Digest of the International Electron Device Meeting 2009, pp. 357-360.
3. D. Sylvester, J.C. Chen, C. Hu "Investigation of Interconnect Capacitance Characterization Using Charge-Based Capacitance Measurement (CBCM) Technique and Three-Dimensional Simulation", IEEE Journal of Solid State Circuits, Volume 33, Issue 3, March 1998 Page(s):449-453.
4. G. Katti, M. Stucchi, K. De Meyer, W. Dehaene "Electrical Modeling & Characterization of Through Silicon Via (TSV) for 3D ICs", IEEE Transactions on Electron Devices, Volume 57, Issue 1, Jan. 2010 Page(s):256-262.