Signal integrity improvements of a MEMS probe card using back-drilling and equalizing techniques

IEEE Transactions on Instrumentation and Measurement

Volumn 60, Issue 3, 2011, Pages 872-879

  Kim, Dong Yeop ^a   Byun, Jindo ^b   Lee, Sang Hoon ^b   Oh, Se Jang ^a   Kang, Ki Sang ^a   Lee, Hai Young ^a  

^a SAMSUNG Electronics   (South Korea)

^b Ajou University   (South Korea)

Author keywords

Back drilling via; double data rate synchronous dynamic random access memory (DDR SDRAM); passive equalizer; probe card; signal integrity (SI); wafer level test

Indexed keywords

BACK-DRILLING VIA; DOUBLE DATA RATE SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY; PASSIVE EQUALIZER; PROBE CARD; SIGNAL INTEGRITY (SI); WAFER-LEVEL TEST;

DYNAMIC RANDOM ACCESS STORAGE; FREQUENCY RESPONSE; JITTER; MICROELECTROMECHANICAL DEVICES; PRINTED CIRCUIT BOARDS; PRINTED CIRCUIT MANUFACTURE; PROBES; SURFACE MOUNT TECHNOLOGY;

DRILLING EQUIPMENT;

EID: 79951593120     PISSN: 00189456     EISSN: None     Source Type: Journal    
DOI: 10.1109/TIM.2009.2036343     Document Type: Article

References (21)

1. C.-G. Hwang, "Semiconductor memories for IT era," in Proc. IEEE ISSCC, Feb. 2002, vol. 1, pp. 24-27.
2. C.-G. Hwang, "Insights on memory technology and the market," IEEE Circuits Devices Mag., vol. 17, no. 3, pp. 12-18, May 2001. (Pubitemid 32684546)
3. R. Pandey and D. Higgins, "P4 probe card-A solution for at-speed, high density, wafer probing," in Proc. IEEE Int. Test Conf., Oct. 1998, pp. 836-842.
4. W. R. Mann, F. L. Taber, P. W. Seitzer, and J. J. Broz, "The leading edge of production wafer probe test technology," in Proc. IEEE Int. Test Conf., Oct. 2004, pp. 1168-1195. (Pubitemid 40610124)
5. B. Leslie and F. Matta, "Wafer-level testing with a membrane probe," IEEE Des. Test. Comput., vol. 6, no. 1, pp. 10-17, Feb. 1989.
6. E. Subramanian and R. Nelson, "Enhanced probe card facilitates at-speed wafer probing in very high density applications," in Proc. IEEE Int. Test Conf., Sep. 1992, pp. 936-939.
7. H. Iwai, A. Nakayama, N. Itoga, and K. Omata, "Cantilever type probe card for at-speed memory test on wafer," in Proc. IEEE VLSI Test Symp., May 2005, pp. 85-89.
8. J. Novitsky and D. Pedersen, "FormFactor introduces an integrated process for wafer-level packaging, burn-in test, and module level assembly," in Proc. IEEE Int. Symp. Adv. Packag. Mater., Mar. 1999, pp. 226-231.
9. S. Choe, S. Tanaka, and M. Esashi, "A matched expansion MEMS probe card with low CTE LTCC substrate," in Proc. IEEE Int. Test Conf., Oct. 2007, pp. 1-6.
10. M. Ozawa and Y. Funatoko, "DDR2 DRAM high-frequency test at probe (HFTAP)," in Proc. IEEE SW Test Workshop, Jun. 2005.
11. G. Back and H. Kilicaslan, "Low force interface for multi-DUT memory and logic application," in Proc. IEEE SW Test Workshop, Jun. 2006.
12. T. Cohen, "Pracrical guidelines for the implementation of back drilling plated through hole vias in multi-gigabit board applications," in Proc. IEC Designcon, 2003, p. 1.
13. S. Camerlo, B. Ahmad, Y. Zou, L. Dang, M. Hu, and S. Priore, "Improving signal integrity of system packaging by back-drilling plated holes in board assembly," in Proc. IEEE Electron. Compon. Technol. Conf., Jun. 2004, vol. 2, pp. 1220-1226.
14. T. Kushata, K. Narita, T. Kaneko, T. Saeki, and H. Tohya, "Resonance stub effect in a transition from a through via hole to a stripline in multilayer PCBs," IEEE Microw. Wireless Compon. Lett., vol. 13, no. 5, pp. 169- 171, May 2003.
15. M. Pajovic, J. Yu, and D. Milojkovic, "Analysis of via capacitance in arbitrary multilayer PCBs," IEEE Trans. Electromagn. Compat., vol. 49, no. 3, pp. 722-726, Aug. 2007.
16. R. Ludwig and P. Bretchko, RF Circuit Design: Theory and Applications. Englewood Cliffs, NJ: Prentice-Hall, 2000.
17. N. Ou, T. Farahmand, A. Kuo, S. Tabatabaei, and A. Ivanov, "Jitter models for the design and test of Gbps-speed serial interconnects," IEEE Des. Test Comput., vol. 21, no. 4, pp. 302-313, Jul. 2004.
18. D. Gizopoulos, Advanced in Electronic Testing: Challenges and Methodologies. Berlin, Germany: Springer-Verlag, 2006.
19. D. K. Cheng, Field andWave Electromagnetics. Reading, MA: Addison- Wesley, 1989.
20. J. Moreira, M. Tsai, J. Kenton, H. Barnes, and D. Faller, "PCB loadboard design challenges for multi-gigabit devices in automated test application," in Proc. IEC Designcon, 2006.
21. J. Liu and X. Lin, "Equalization in high-speed communication systems," IEEE Circuits Syst. Mag., vol. 4, no. 2, pp. 4-17, Sep. 2004.