Equalization in high-speed communication systems

IEEE Circuits and Systems Magazine

Volumn 4, Issue 2, 2004, Pages 4-17

  Liu, Jin ^a   Lin, Xiaofeng ^a  

^a The University of Texas at Dallas   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BANDPASS FILTERS; DATA COMMUNICATION SYSTEMS; ERROR CORRECTION; NATURAL FREQUENCIES; PRINTED CIRCUIT BOARDS; SIGNAL INTERFERENCE; SIGNAL PROCESSING; COMPUTER APPLICATIONS; NETWORKS (CIRCUITS);

CHROMATIC DISPERSION (CD); CLOCK AND DATA RECOVERY (CDR); INTER-SYMBOL-INTERFERENCE (ISI); POLARIZATION MODE DISPERSION (PMD);

TELECOMMUNICATION; DATA COMMUNICATION SYSTEMS;

CLOCK AND DATA RECOVERY; DATA TRANSMISSION RATES; FREQUENCY DISPERSION; HIGH FREQUENCY HF; HIGH-SPEED COMMUNICATION SYSTEMS; RECEIVER EQUALIZATION; TRANSMISSION DISTANCES; TRANSMISSION MEDIA;

EID: 4043100510     PISSN: 1531636X     EISSN: None     Source Type: Journal    
DOI: 10.1109/MCAS.2004.1330746     Document Type: Article

References (67)

1. J.N. Babanezhad, "A 3.3 V analog adaptive line-equalizer for fast Ethernet data communication," in Proc. IEEE Custom Integrated Circuits Conf., 1998, pp. 343-346.
2. J. Cioffi, W. Abbott, H. Thapar, C. Melas, and K. Fisher, "Adaptive equalization for magnetic-disk storage channels," IEEE Comm. Mag., vol. 28, pp. 14-29, Feb. 1990.
3. M. Shtaif, "Modeling and analysis of digital optical communications systems," in Encyclopedia of Telecommunications, J.G. Proakis, Ed. New York: Wiley, 2003.
4. H. Wu and J. Tierno, et al., "Differential 4-tap and 7-tap transverse filters in SiGe for 10 Gb/s multimode fiber optic link equalization," in ISSCC Digest of Technical Papers, pp. 180-181, 2003.
5. H. Johnson and M. Graham, High-Speed Signal Propagation-Advanced Black Magic. Englewood Cliffs, NJ: Prentice Hall, 2003.
6. W.J. Dally and J.W. Poulton, Digital Systems Engineering, Cambridge: Cambridge University Press, 1998.
7. J.G. Proakis, Digital Communications, 4th ed., McGraw-Hill Higher Education, 2000.
8. S.H. Hall, G.W. Hall, and J.A. McCall, High-Speed Digital System Design, John Wiley & Sons, Inc., 2000.
9. M.I. Montrose, EMC and the Printed Circuit Board: Design, Theory, and Layout Made Simple, Piscataway, NJ: IEEE, 1998.
10. I. Kalet and S. Shamai, "On the capacity of twisted wire pair: Gaussian model," IEEE Trans. Comm., vol. 38, pp. 379-383, March 1990.
11. Workshop on Analog Telecom and Circuit Concepts, ISSCC, Feb. 2003.
12. J.T. Stonick, G.-Y. Wei, J.L. Sonntag, and O.K. Weinlader, "An adaptive PAM-4 5-Gb/s backplane transceiver in 0.25-μm CMOS," IEEE J. Solid-state Circuits, vol. 38, no. 3, pp. 436-443, March 2003.
13. W.J. Dally and J. Poulton, "Transmitter equalization for 4-Gbps signaling," IEEE Micro, pp. 48-56, Jan./Feb. 1997.
14. A. Fiedler, R. Mactaggart, J. Welch, and S. Krishnan, "A 1.0625 Gbps transceiver with 2x-oversampling and transmit signal pre-emphasis," in ISSCC Digest of Technical Papers, pp. 238-239, Feb. 1997.
15. D.J. Foley and M.P. Flynn, "A low-power 8-PAM serial transceiver in 0.5-μm digital CMOS," IEEE J. Solid-state Circuits, vol. 37, no. 3, pp. 310-316, March 2002.
16. R. Farjad-Rad, C.-K. K. Yang, M. Horowitz, and T. H. Lee, "A 0.3 μm CMOS 8-Gb/s 4-PAM serial link transceiver," IEEE J. Solid-state Circuits, vol. 35, pp. 757-764, May 2000.
17. R. Farjad-Rad, C.-K. K. Yang, M. Horowitz, and T. H. Lee, "A 0.4 μm CMOS 8-Gb/s 4-PAM serial link transceiver," IEEE J. Solid-state Circuits, vol. 35, pp. pp. 580-585, May 1999.
18. Maxim Integrated Products, "Designing a simple, small, wide-band and low-power equalizer for FR4 copper links," DesignCon, 2003.
19. J. Addis and B. Hoffer, "Feedbeside amplifier," U.S. Patent: 4,132,958, 1979.
20. Maxim Integrated Products, "MAX3800: 3.2 Gbps Adaptive Equalizer and Cable Driver," 2001.
21. Y. Kudoh, M. Fukaishi, and M. Mizuno, "A 0.13 μm CMOS 5-Gb/s 10-m 28 AWG cable transceiver with no-feedback-loop continuous-time post-equalizer," IEEE J. Solid-state Circuits, vol. 38, no. 5, pp. 741-746, May 2003.
22. Y. Tsividis, Z. Czarnul, and S.C. Fang, "MOS transconductors with high linearity," Electron. Lett., vol. 22, pp. 245-246, Feb. 1986.
23. J. Choi, M. Hwang, and D. Jeong, "A CMOS 3.5 Gbps continuous-time adaptive cable equalizer with joing adaptation method of low-frequency gain and high-frequency boosting," in VLSI Technology Symp. Dig. Tech. Papers, pp. 103-106, 2003.
24. R. Farjad-Rad and H.-T. Ng, et al., "0.622-8.0 Gbps 150 mW serial 10 macrocell with fully flexible preemphasis and equalization," in VLSI Technology Symp. Dig. Tech. Papers, pp. 63-66, 2003.
25. J.E.C. Brown, P.J. Hurst, and L. Der, "A 35 Mb/s mixed-signal decision-feedback equalizer for disk drives in 2-um CMOS," IEEE J. Solid-State Circuits, vol. 31, no. 9, pp. 1258-1266, Sept. 1996.
26. R. Gomez, M. Rofougaran, and A.A. Abidi, "A discrete-time analog signal processor for disk read channels," in ISSCC Digest of Technical Papers, pp. 212-213, 1993.
27. P.K.D. Pai, A.D. Brewster, and A.A. Abidi, "A 160-MHz analog frontend IC for EPR-IV PRML magnetic storage read channels," IEEE J. Solid-State Circuits, vol. 31, no. 11, pp. 1803-1816, Nov. 1996.
28. C.J. Nicol, P. Larsson, K. Azadet, and J.H. O'Neil, "A low-power 128-tap digital adaptive equalizer for broadband modems," IEEE J. Solid-State Circuits, vol. 32, no. 11, pp. 1777-1789, Nov. 1997.
29. C.S.H. Wong, J.C. Rudell, G.T. Uehara, and P.R. Gray, "A 50 MHz eighttap adaptive equalizer for partial-response channels," IEEE J. Solid-State Circuits, vol. 30, no. 3, pp. 228-234, March 1995.
30. S. Rylov and A. Rylyakov, et al., "A 2.3 Gsample/s 10-tap digital FIR filter for magnetic recording read channels," in ISSCC Digest of Technical Papers, pp. 190-191, 2001.
31. R. Staszewski, K. Muhammad, and P. Balsara, "A 550 Msample/s 8-tap FIR digital filter for magnetic recording read channels," in ISSCC Digest of Technical Papers, pp. 80-81, 2000.
32. J.E.C. Brown, P.J. Hurst, and L. Der, "A 35 Mb/s mixed-signal decision-feedback equalizer for disk drives in 2-um CMOS," IEEE J. Solid-State Circuits, vol. 31, no. 9, pp. 1258-1266, Sept. 1996.
33. S. Kiriaki and T.L. Viswanathan, et al., "A 160-MHz analog equalizer for magnetic disk read channels," IEEE J. Solid-State Circuits, vol. 32, no. 11, pp. 1839-1850, Nov. 1997.
34. J. Sonntag, O. Agazzi, and P. Aziz, et al., "A high-speed, low power PRML read channel device," IEEE Trans. Magnetics, vol. 31, no. 2, pp. 1186-1195, March 1995.
35. D. Xu, Y. Song, and G.T. Uehara, "A 200 MHz 9-tap analog equalizer for magnetic disk read channels in 0.6 um CMOS," in ISSCC Digest of Technical Papers, pp. 74-75, 1996.
36. X. Wang and R.R. Spencer, "A low-power 170-MHz discrete-time analog FIR filter," IEEE J. Solid-State Circuits, vol. 36, no. 5, pp. 816-822, May 2001.
37. Y.L. Cheung and A. Buchwald, "A sampled-data switched-current analog 16-tap FIR filter with digitally programmable coefficients in 0.8 μm CMOS," in ISSCC Digest of Technical Papers, pp. 54-55, 1997.
38. T.-C. Lee and B. Razavi, "A 125-MHz CMOS mixed-signal equalizer for Gigabit Ethernet on copper wire," in Proc. IEEE Custom Integrated Circuits Conf., 2001, pp. 131-134.
39. G.T. Uehara and P.R. Gray, "Parallelism in analog and digital PRML magnetic disk read channel equalizers," IEEE Trans. Magnetics, vol. 31, no. 2, pp. 1174-1179, 1995.
40. Z. Ciota, A. Napieralski, and J. L. Noullet, "Analogue realisation of integrated FIR fillers," IEE Proc.-Circuits Devices Syst., vol. 143, no. 5, pp. 274-281, 1996.
41. N.P. Kelly, D.L. Ray, and D.W. Vogel, "A mixed-signal DFE/FFE receiver for 100Base-TX applications," in ISSCC Digest of Technical Papers, pp. 310-311, 2000.
42. K. Gotoh and H. Tamura. et al., "A 2B parallel 1.25 Gb/s interconnect I/O interface with self-configurable link and plesiochronous clocking," in ISSCC Digest of Technical Papers, pp. 180-181, 1999.
43. H. Tamura and M. Saito, et al., "Partial response detection technique for driver power reduction in high-speed memory-to-processor communications," in. ISSCC Digest of Technical Papers, pp. 342-343, 1997.
44. J.-Y. Sim and J.-J. Nam, et al., "A CMOS transceiver for DRAM bus system with a demultiplexed equalization scheme," IEEE J. Solid-State Circuits, vol. 37, no. 2, pp. 245-250, Feb. 2002.
45. N.P. Sands and M.W. Hauser, et al., "A 200 Mb/s analog DFE read channel," in ISSCC Digest of Technical Papers, pp. 72-73, 1996.
46. R. Alini and G. Betti, et al., "A 200-MSample/s trellis-coded PRML read/write channel with analog adaptive equalizer and digital servo," IEEE J. Solid-State Circuits, vol. 32, no. 11, pp. 1824-1838, Nov. 1997.
47. X. Lin and J. Liu. "A CMOS continuous-time FIR filter for 1 Gbps cable equalizer," in Proc. ISCAS, May 2003, pp. 296-299.
48. E. Burlingame and R. Spencer, "An analog CMOS high-speed continuous-time FIR filter," in Proc. Euro. Solid-Stale Circuits (ESSCIRC), 2000.
49. T.T.Y. Wang, Fundamentals of Distributed Amplification. Boston, MA: Artech, 1993.
50. H. Ahn and D.J. Allstot, "A 0.5-8.5-GHz differential CMOS distributed amplifier," IEEE J. Solid-State Circuits, vol. 37, no. 8, pp. 985-993, Aug. 2002.
51. J.W.M. Bergman, Digital Baseband Transmission and Recording, Dordrecht: Kluwer, 1996.
52. E.A. Lee and D.G. Messerschmitt, Digital Communication, Dordrecht: Kluwer, 1994.
53. M. Le, P. Hurst, and K. Dyer, "An analog DFE for disk drives using a mixed-signal integrator," IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 592-598, May 1999.
54. A. Shoval, D.A. Johns, and W.M. Snelgrove, "Comparison of DC offset effects in four LMS adaptive algorithms," IEEE Trans. Circuits Syst. II, vol. 42, no. 3, pp. 176-185, March 1995.
55. J.R. Treichler, C.R. Johnson, Jr., and M.G. Larimore, Theory and Design of Adaptive Filters, Englewood Cliffs, NJ: Prentice Hall, 2001.
56. A. Shoval, O. Shoaei, K. Lee, and R. Leonwich, "A CMOS mixed-signal 100 Mb/s receive architecture for fast ethernet," in Proc. IEEE Custom Integrated Circuits Conf., 1999, pp. 253-256.
57. M. Altmann, J.M. Caia, R. Morle, M. Dunsmore, Y. Xie, and N. Kocaman, "A low-power CMOS 155 Mb/s transceiver for SONET/SDH over co-ax & fibre," in Proc. IEEE Custom Integrated Circuits Conf., 2001, pp. 127-130.
58. T. Ellermeyer, U. Langmann, B. Wedding, and W. Pöhlmann, "A 10 Gb/s eye opening monitor IC for decision-guided optimization of the frequency response of an optical receiver," in ISSCC Digest of Technical Papers, pp. 50-51, 2000.
59. A.J. Baker, "An adaptive cable equalizer for serial digital video rates to 400 Mb/s," in ISSCC Digest of Technical Papers, pp. 174-175, 1996.
60. S. Gondi, R. Geiger, J. Liu, J. Bareither, S. Sterrantino, and E. Pace, "A 2v low-power CMOS 125 Mbaud repeater architecture for UTP5 cables," in Proc. Euro. Solid-State Circuits (ESSCIRC), 2002, pp. 571-574.
61. X. Lin, J. Liu, and J. Fonseka, "A High speed low-noise equalization technique with improved bit error rate," in Proc. ISCAS, May 2002, pp. 564-567.
62. G.P. Hartman, K.W. Martin, and A. Mclaren, "Continuous-time adaptive-analog coaxial cable equalizer in 0.5 μm CMOS," in Proc. ISCAS, 1999, pp. 97-100.
63. M.H. Shakiba, "A 2.5 Gb/s adaptive cable equalizer," in SSSCC Digest of Technical Papers, pp. 396-397, 1999.
64. T. Bakken and J. Choma, "Stability of a continuous-time state variable filter with Op-amp and OTA-C integrators," in Proc. Eighth Great Lakes Symp. on VLSI, 1998, pp. 77-82.
65. S. Pipilos and Y. Tsividis, "Design of active RLC integrated filters with applications in the GHz range," Electronics Letters, vol. 30, pp. 472-474, Mar. 1994.
66. C.Y. Wu and S.Y. Hsiao, "The design of a 3-V 900-MHz CMOS bandpass amplifier," IEEE J. Solid-State Circuits, vol. 32, no. 2, pp. 159-168, Feb. 1997.
67. X. Lin and J. Liu, "Pulse extraction: A digital power spectrum estimation method for adaptation of Gbps equalizers," in Proc. ISCAS, May 2003, pp. 749-752.