FormFactor introduces an integrated process for wafer-level packaging, burn-in test, and module level assembly

Proceedings - International Symposium on Advanced Packaging Materials: Processes, Properties and Interfaces

Volumn , Issue , 1999, Pages 226-231

  Novitsky, J ^a   Pedersen, D ^a  

^a FORMFACTOR INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP SCALE PACKAGES; INTERFACES (MATERIALS); PACKAGING MATERIALS; SEMICONDUCTOR DEVICE MANUFACTURE; SILICON WAFERS;

BACK-END PROCESSING; CONNECTION ELEMENT; COST MODELING; INCREASING COSTS; PROBABILITY OF SUCCESS; SEMICONDUCTOR MANUFACTURING; WAFER LEVEL PACKAGING; WAFER SINGULATION;

ELECTRONICS PACKAGING;

EID: 0345302935     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISAPM.1999.757317     Document Type: Conference Paper

References (0)