Analysis of via capacitance in arbitrary multilayer PCBs

IEEE Transactions on Electromagnetic Compatibility

Volumn 49, Issue 3, 2007, Pages 722-726

  Pajovic, Miroslasv ^a   Yu, Jinghan ^a   Milojkovic, Dragan ^a  

^a CISCO SYSTEMS   (United States)

Author keywords

Lumped circuit models for vias; Signal layer transitions in multilayer printed circuit boards; Signal line discontinuities; Via parasitics

Indexed keywords

ARBITRARY MULTILAYERS; COMPUTATIONAL CALCULATIONS; HIGH-SPEED SIGNALS; LABORATORY MEASUREMENTS; LCR METERS; LUMPED CIRCUIT MODELS FOR VIAS; PARASITIC CAPACITANCES; SIGNAL INTEGRITIES; SIGNAL LAYER TRANSITIONS IN MULTILAYER PRINTED CIRCUIT BOARDS; SIGNAL LINE DISCONTINUITIES; THROUGH HOLES; TRANSMISSION-LINE MODELING METHODS; VECTOR NETWORK ANALYZERS; VIA PARASITICS;

CAPACITANCE; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK ANALYZERS; ELECTROMAGNETIC COMPATIBILITY; ELECTROMAGNETIC WAVE EMISSION; LUMPED PARAMETER NETWORKS; MICROSTRIP LINES; MULTILAYERS; POWER CONVERTERS; PRINTED CIRCUIT MANUFACTURE; SIGNAL PROCESSING; TRANSMISSION LINE THEORY; TRANSMISSION NETWORK CALCULATIONS;

PRINTED CIRCUIT BOARDS;

EID: 51649123553     PISSN: 00189375     EISSN: None     Source Type: Journal    
DOI: 10.1109/TEMC.2007.902382     Document Type: Article

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