Insights on memory technology and the market

IEEE Circuits and Devices Magazine

Volumn 17, Issue 3, 2001, Pages 12-18

  Hwang, Chang Gyu ^a,b  

^a SAMSUNG Electronics   (South Korea)

^b IEEE   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

MOORE'S LAW;

CELLULAR TELEPHONE SYSTEMS; DATA TRANSFER; DYNAMIC RANDOM ACCESS STORAGE; FLASH MEMORY; INTERFACES (COMPUTER); NANOTECHNOLOGY; PROCESS CONTROL; SEMICONDUCTOR DEVICE MANUFACTURE; STATIC RANDOM ACCESS STORAGE;

SEMICONDUCTOR STORAGE;

EID: 0035328484     PISSN: 87553996     EISSN: None     Source Type: Journal    
DOI: 10.1109/101.933787     Document Type: Article

References (12)

1. The current and future status of the memory market and technology
2. 0.13 um DRAM technology for giga-bit density stand-alone and embedded DRAMs
3. Feasibility of very low k1 (=0.31) KrF lithography
4. CMOS device scaling beyond 100 nm
5. Si-doped aluminates for high temperature metal-gate CMOS: Zr-Al-Si-O, a novel gate dielectric for low power applications
6. Damascene metal gate MOSFETs with Co silicided source/drain and high-k gate dielectrics
7. Architecture of SOI transistors: What's next?
8. A self-aligned stacked capacitor using novel Pt electroplating method for 1 Gbit DRAMs and beyond
9. 5/CVD-TiN capacitor for multi-gigabit-scale DRAM generation
10. Advanced interconnect schemes towards 0.1 μm
11. A high performance 0.13 μm SOI CMOS technology with Cu interconnects and low-k BEOL dielectric
12. A single-electron shut-off transistor for a scalable sub-0.1 μm memory