Hierarchical fault tolerance for nanoscale memories

IEEE Transactions on Nanotechnology

Volumn 5, Issue 4, 2006, Pages 407-414

  Jeffery, Casey M ^b   Figueiredo, Renato J O ^a,b  

^a IEEE   (United States)

^b University of Florida   (United States)

Author keywords

Electronic nanotechnology; Memory architecture; Memory fault tolerance; Molecular electronics

Indexed keywords

ELECTRONIC NANOTECHNOLOGY; MEMORY ARCHITECTURE; MEMORY FAULT TOLERANCE; MOLECULAR ELECTRONICS;

BIT ERROR RATE; COMPUTER SIMULATION; FAULT TOLERANT COMPUTER SYSTEMS; HIERARCHICAL SYSTEMS;

NANOTECHNOLOGY;

EID: 33746281393     PISSN: 1536125X     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNANO.2006.877431     Document Type: Article

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