Allocation of Multiport Memories in Data Path Synthesis

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 7, Issue 4, 1988, Pages 536-540

  Balakrishnan, M ^a   Majumdar, Arun K ^b   Banerji, Dilip K ^b   Linders, James G ^b   Majithia, Jayanti C ^b  

^a SYRACUSE UNIVERSITY   (United States)

^b UNIVERSITY OF GUELPH   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE - OPTIMIZATION; COMPUTER INTERFACES;

DATA PATH SYNTHESIS; INTERCONNECTIONS MINIMIZATION; MULTIBUS ARCHITECTURE; MULTIPORT MEMORIES ALLOCATION;

COMPUTER SYSTEMS, DIGITAL;

EID: 0023998697     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.3188     Document Type: Article

References (7)

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