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Volumn 12, Issue 9, 1993, Pages 1266-1278

Global Optimization Approach for Architectural Synthesis

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; COMPUTER ARCHITECTURE; HEURISTIC PROGRAMMING;

EID: 0027660748     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.240074     Document Type: Article
Times cited : (44)

References (25)
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  • 6
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    • Hafer, L.1    Parker, A.2
  • 8
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    • A new integer linear programming formulation for the scheduling problem in data path synthesis
    • J. Lee, Y. Hsu, and Y. Lin, “A new integer linear programming formulation for the scheduling problem in data path synthesis,” in Inti. Conf. Proc. Computed Aided Design, 1989.
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    • Lee, J.1    Hsu, Y.2    Lin, Y.3
  • 10
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    • Automated datapath synthesis: A compilation approach
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    • (1987) Processing and Microprogramming , vol.21 , pp. 577-584
    • Pfahler, P.1
  • 11
    • 0020815626 scopus 로고
    • Solving large scale zero-one linear programming problems
    • Sept.
    • H. Crowder, E. L. Johnson, and M. Padberg, “Solving large scale zero-one linear programming problems,” Op. Res., vol. 31, no. 5, pp. 803–834, Sept. 1983.
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    • Crowder, H.1    Johnson, E.L.2    Padberg, M.3
  • 13
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    • A global optimization approach to architectural synthesis of VLSI Digital synchronous systems with analog and asynchronous interfaces
    • July
    • C. H. Gebotys, “A global optimization approach to architectural synthesis of VLSI Digital synchronous systems with analog and asynchronous interfaces,” Ph.D. thesis, Dept. ECE, University of Waterloo, July 1991.
    • (1991) Ph.D. thesis, Dept. ECE, University of Waterloo
    • Gebotys, C.H.1
  • 15
    • 0026139605 scopus 로고
    • A formal approach to the scheduling problem in high-level synthesis
    • C.T. Hwang, J.H., and Y.C. Hsu, “A  formal approach to the scheduling problem in high-level synthesis,” IEEE Trans. Computer Aided Design, vol. CAD-10, no, 4, pp. 464–475, 1991.
    • (1991) IEEE Trans. Computer Aided Design , vol.CAD-10 , Issue.4 , pp. 464-475
    • Hwang, C.T.1    Lee, J.H.2    Hsu, Y.C.3
  • 16
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    • Tutorial on high level synthesis
    • A. Parker, “Tutorial on high level synthesis,” in Can. Conf. on VLSI, 1991.
    • (1991) Can. Conf. on VLSI
    • Parker, A.1
  • 17
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    • Path based scheduling for synthesis
    • R. Camposano, “Path based scheduling for synthesis,” IEEE Trans. Computer-Aided Design, vol. CAD-10, pp. 85–93, 1991.
    • (1991) IEEE Trans. Computer-Aided Design , vol.CAD-10 , pp. 85-93
    • Camposano, R.1
  • 18
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    • Architectural partitioning for systems level design of integrated circuits
    • Pittsburgh, PA
    • E. D. Lagnese, “Architectural partitioning for systems level design of integrated circuits,” Ph.D. thesis, CMUCAD-89-27, Carnegie-Mellon University, Pittsburgh, PA, 1989.
    • (1989) Ph.D. thesis, CMUCAD-89-27, Carnegie-Mellon University
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  • 19
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    • Gebotys, C.H.1    Elmasry, M.I.2
  • 23
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  • 24
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.