-
2
-
-
0009601410
-
An integrated automatic layout generation system
-
July
-
J. Rabaey, S. Pope, and R. Brodersen, “An integrated automatic layout generation system,” IEEE Trans. Computer-Aided Design, vol. CAD-4, pp. 285–296, July 1985.
-
(1985)
IEEE Trans. Computer-Aided Design
, vol.4 CAD
, pp. 285-296
-
-
Rabaey, J.1
Pope, S.2
Brodersen, R.3
-
3
-
-
0022705701
-
Computer generation of digital filter banks
-
Apr.
-
P. Ruetz et al., “Computer generation of digital filter banks,” IEEE Trans. Computer-Aided Design, vol. CAD-5, pp. 256–265, Apr. 1986.
-
(1986)
IEEE Trans. Computer-Aided Design
, vol.5 CAD
, pp. 256-265
-
-
Ruetz, P.1
-
4
-
-
84936304303
-
First results and design experience with silicon compiler ALGIC
-
New York: IEEE Press, Nov.
-
J. Schuck, M. Glesner, and M. Lacken, “First results and design experience with silicon compiler ALGIC,” in VLSI Signal Processing II. New York: IEEE Press, Nov. 1986.
-
(1986)
VLSI Signal Processing II
-
-
Schuck, J.1
Glesner, M.2
Lacken, M.3
-
5
-
-
0022982645
-
SPIL: A silicon compiler with performance evaluation
-
Nov.
-
B. Petersen, B. White, D. Solomon, and M. Elmasry, “SPIL: A silicon compiler with performance evaluation,” in Proc. ICCAD, pp. 500–503, Nov. 1986.
-
(1986)
Proc. ICCAD
, pp. 500-503
-
-
Petersen, B.1
White, B.2
Solomon, D.3
Elmasry, M.4
-
6
-
-
79954499635
-
HAL: A multi-paradigm approach to automatic data path synthesis
-
P. Paulin, J. Knight, and E. Gyrczyc, “HAL: A multi-paradigm approach to automatic data path synthesis,” in Proc. 23rd Design Automation Conf., pp. 263–270, 1986.
-
(1986)
Proc. 23rd Design Automation Conf.
, pp. 263-270
-
-
Paulin, P.1
Knight, J.2
Gyrczyc, E.3
-
7
-
-
0023983163
-
Sehwa: A software package for synthesis of pipelines from behavioral specifications
-
Mar.
-
N. Park and A. Parker, “Sehwa: A software package for synthesis of pipelines from behavioral specifications,” IEEE Trans. Computer-Aided Design, vol. 7, pp. 356–370, Mar. 1988.
-
(1988)
IEEE Trans. Computer-Aided Design
, vol.7
, pp. 356-370
-
-
Park, N.1
Parker, A.2
-
8
-
-
84937812345
-
Using bottom up design techniques in synthesis of digital hardware from abstract behavioral descriptions
-
M. McFarland, “Using bottom up design techniques in synthesis of digital hardware from abstract behavioral descriptions,” in Proc. 23rd Design Automation Conf., pp. 474–480, 1986.
-
(1986)
Proc. 23rd Design Automation Conf.
, pp. 474-480
-
-
McFarland, M.1
-
10
-
-
85050214309
-
MAHA: A program for data path synthesis
-
A. Parker, J. Pizarro, and M. Mlinon, “MAHA: A program for data path synthesis,” in 23rd Design Automation Conf. 86, pp. 461–466, 1986.
-
(1986)
23rd Design Automation Conf. 86
, pp. 461-466
-
-
Parker, A.1
Pizarro, J.2
Mlinon, M.3
-
11
-
-
0022989383
-
State synthesis & connectivity binding for microarchitecture compilation
-
Nov.
-
B. Pangrie and D. Gajski, “State synthesis & connectivity binding for microarchitecture compilation,” in Proc. ICCAD86, Nov. 1986.
-
(1986)
Proc. ICCAD86
-
-
Pangrie, B.1
Gajski, D.2
-
12
-
-
84941473086
-
A CAD methodology for mapping DSP Algorithms onto MP custom architectures
-
May
-
G. Goesens et al., “A CAD methodology for mapping DSP Algorithms onto MP custom architectures,” in Proc. IEEE ICCAS 86, May 1986.
-
(1986)
Proc. IEEE ICCAS 86
-
-
Goesens, G.1
-
13
-
-
0343329589
-
CATHEDRAL-II: A synthesis system for multiprocessor DSP systems
-
D. Gajsk, Ed. Reading, MA: Addison-Wesley
-
J. Rabaey, H. De Man, J. Vanhoof, G. Goosens, and F. Catthoor, “CATHEDRAL-II: A synthesis system for multiprocessor DSP systems,” in Silicon Compilation, D. Gajsk, Ed. Reading, MA: Addison-Wesley, pp. 311–360, 1988.
-
(1988)
Silicon Compilation
, pp. 311-360
-
-
Rabaey, J.1
De Man, H.2
Vanhoof, J.3
Goosens, G.4
Catthoor, F.5
-
14
-
-
0347372133
-
Parallel bit-level pipelined VLSI design for high speed signal processing
-
Sept.
-
M. Hatamian and G. Cash, “Parallel bit-level pipelined VLSI design for high speed signal processing,” Proc. IEEE, vol. 75, pp. 11921202, Sept. 1987.
-
(1987)
Proc. IEEE
, vol.75
, pp. 1192-1202
-
-
Hatamian, M.1
Cash, G.2
-
15
-
-
0022102734
-
Synchronizing large VLSI processor arrays
-
Aug.
-
A. Fisher and H. Kung, “Synchronizing large VLSI processor arrays,” IEEE Trans. Computers, vol. C-33, pp. 734–740, Aug. 1985.
-
(1985)
IEEE Trans. Computers
, vol.33 C
, pp. 734-740
-
-
Fisher, A.1
Kung, H.2
-
16
-
-
0021989894
-
Computer architecture for DSP
-
May
-
J. Allen, “Computer architecture for DSP,” Proc. IEEE, vol. 73, pp. 852–873, May 1985.
-
(1985)
Proc. IEEE
, vol.73
, pp. 852-873
-
-
Allen, J.1
-
17
-
-
0016920380
-
Realisability of digital filter networks
-
A. Fettweis, “Realisability of digital filter networks,” AEU, vol. 30, 1976.
-
(1976)
AEU
, vol.30
-
-
Fettweis, A.1
-
18
-
-
84939698077
-
Synchronous data flow
-
Sept.
-
E.A. Lee and D.G. Messerschmitt, “Synchronous data flow,” Proc. IEEE, vol. 75, pp. 1235–1245, Sept. 1987.
-
(1987)
Proc. IEEE
, vol.75
, pp. 1235-1245
-
-
Lee, E.A.1
Messerschmitt, D.G.2
-
19
-
-
84941473563
-
-
Tech. Rep. UW/ICR 88–06, Univ. Waterloo, Canada
-
B. Haroun and M.I. Elmasry, “SPAID,” Tech. Rep. UW/ICR 88–06, Univ. Waterloo, Canada, 1988.
-
(1988)
SPAID
-
-
Haroun, B.1
Elmasry, M.I.2
-
20
-
-
0022756374
-
Automated synthesis of data paths in digital systems
-
July
-
C. Tseng and P. Seviourek, “Automated synthesis of data paths in digital systems,” IEEE Trans. Computer-Aided Design, pp. 379–395, July 1986.
-
(1986)
IEEE Trans. Computer-Aided Design
, pp. 379-395
-
-
Tseng, C.1
Seviourek, P.2
-
21
-
-
84941472360
-
Optical implementation of flow graphs on synchronous multiprocessors
-
T. Barnwell III and D. Schwarz, “Optical implementation of flow graphs on synchronous multiprocessors,” in Int. Conf. on ASSP 84. 1984.
-
(1984)
Int. Conf. on ASSP 84
-
-
Barnwell, T.1
Schwarz, D.2
-
22
-
-
11844277920
-
Cyclo static solution: Optimal multipr realisation of recursive algorithms
-
New York: IEEE Press. Nov.
-
D. Schwartz and T. Barnwell III, “Cyclo static solution: Optimal multipr realisation of recursive algorithms.” in VLSI Signal Processing II. New York: IEEE Press. Nov. 1986.
-
(1986)
VLSI Signal Processing II
-
-
Schwartz, D.1
Barnwell, T.2
-
23
-
-
0020504458
-
Optimising synchronous circuitry by retiming
-
Computer Sci. Press.
-
F. Rose, C. Lciscrson, and J. Saxe, “Optimising synchronous circuitry by retiming.” in Proc. Caltech Conf on VLSI. pp. 41–67. Computer Sci. Press. 1983.
-
(1983)
Proc. Caltech Conf on VLSI.
, pp. 41-67
-
-
Rose, F.1
Lciscrson, C.2
Saxe, J.3
-
25
-
-
84941474909
-
A graph theoretic technique for the generation of systolic implementation
-
D. Schwartz and T. Barnwell III. “A graph theoretic technique for the generation of systolic implementation.” in Proc. Asilomar Conf. on CAS 84. 1984
-
(1984)
Proc. Asilomar Conf. on CAS 84.
-
-
Schwartz, D.1
Barnwell, T.2
-
26
-
-
84990479742
-
An eflicient heuristic procedure for partitioning graphs
-
Feb.
-
B. Kernighan and S. Lin. “An eflicient heuristic procedure for partitioning graphs.” Bell Syst. Tech. J. pp. 291–307, Feb. 1970.
-
(1970)
Bell Syst. Tech. J.
, pp. 291-307
-
-
Kernighan, B.1
Lin, S.2
-
28
-
-
0020542625
-
Methodical aspects of logic synthesis
-
vol., Jan. 83.
-
H. Lipp. “Methodical aspects of logic synthesis.” Proc. IEEE. vol. 71, vol. pp. 88–97. Jan. 83.
-
Proc. IEEE.
, vol.71
, pp. 88-97
-
-
Lipp, H.1
-
29
-
-
84941461367
-
An optimizer for hardware synthesis
-
Winter
-
J. Bhasker. “An optimizer for hardware synthesis.” Scientific Honeyweller, pp. 23–34, Winter 1987.
-
(1987)
Scientific Honeyweller
, pp. 23-34
-
-
Bhasker, J.1
-
30
-
-
0023312914
-
Flamel: A highlevel hardware compiler
-
Mar.
-
H. Trickey, “Flamel: A highlevel hardware compiler.” IEEE Trans. Computer-Aided Design, vol. CAD-6, pp. 259–269, Mar. 1987.
-
(1987)
IEEE Trans. Computer-Aided Design
, vol.6 CAD
, pp. 259-269
-
-
Trickey, H.1
-
32
-
-
84939342111
-
System timing
-
C. Mead and L. Conway, Eds. Reading, MA: Addison-Wesley
-
C. Seitz. “System timing.” in Introduction to VLSI Systems. C. Mead and L. Conway, Eds. Reading, MA: Addison-Wesley, 1981.
-
(1981)
Introduction to VLSI Systems
-
-
Seitz, C.1
-
33
-
-
0016920527
-
Anomalous response times of input synchronizers
-
Feb.
-
M. Pechoucek. “Anomalous response times of input synchronizers.” IEEE Trans. Computers, vol. C-25, pp. 133–139. Feb. 1976.
-
(1976)
IEEE Trans. Computers
, vol.25 C
, pp. 133-139
-
-
Pechoucek, M.1
-
34
-
-
0020716303
-
Optimising synchronous systems
-
no. 1.
-
C. Leiserson and J. Saxe. “Optimising synchronous systems.” J. VLSI & Comp. Syst., vol. 1. no. 1. pp. 41–67. 1983.
-
(1983)
J. VLSI & Comp. Syst.
, vol.1
, pp. 41-67
-
-
Leiserson, C.1
Saxe, J.2
-
35
-
-
84879653525
-
Designing self timed systems
-
Sept.
-
A. Yakovlev, “Designing self timed systems.” VLSI System Design. pp. 70–86, Sept. 1985.
-
(1985)
VLSI System Design
, pp. 70-86
-
-
Yakovlev, A.1
-
36
-
-
0003859414
-
-
Englewood Clifts. NJ: Prentice Hall.
-
S.Y. Kung, VLSI Array Processors. Englewood Clifts. NJ: Prentice Hall. 1988.
-
(1988)
VLSI Array Processors
-
-
Kung, S.Y.1
-
39
-
-
0001430010
-
Parallel sequencing and assemblv line problems
-
T.C. Hu. “Parallel sequencing and assemblv line problems.” Oper. Res., vol. 9, pp. 841–848. 1961.
-
(1961)
Oper. Res.
, vol.9
, pp. 841-848
-
-
Hu, T.C.1
-
40
-
-
0023230724
-
Force-directed scheduling in automatic data path synthesis
-
P. Paulin and J. Knight, “Force-directed scheduling in automatic data path synthesis,” in ACM/IEEE 24th DAC, 1987.
-
(1987)
ACM/IEEE 24th DAC
-
-
Paulin, P.1
Knight, J.2
-
42
-
-
84941479439
-
-
New York: Elsevier Sci.
-
Claude Berge, Graphs. New York: Elsevier Sci., 1985.
-
(1985)
Claude Berge, Graphs
-
-
-
43
-
-
0001118054
-
Algorithms for edge coloring bipartite graphs and multigraphs
-
Feb.
-
H. Gabow and O. Kariv. “Algorithms for edge coloring bipartite graphs and multigraphs.” SIAM J. Comput. vol. 11, pp. 117–129, Feb. 1982.
-
(1982)
SIAM J. Comput.
, vol.11
, pp. 117-129
-
-
Gabow, H.1
Kariv, O.2
-
45
-
-
84987006716
-
An optimum channel routing algorithm for polycell layouts of integrated circuits
-
B. Kernighan. D. Schweikert. and G. Persky. “An optimum channel routing algorithm for polycell layouts of integrated circuits.” in Proc. 10th Design Automation Conf., pp. 50–59, 1973.
-
(1973)
Proc. 10th Design Automation Conf.
, pp. 50-59
-
-
Kernighan, B.1
Schweikert, D.2
Persky, G.3
-
46
-
-
0018547323
-
An optimal solution for channel assignment problem
-
Nov.
-
U. Gupta, D. Lee, and J. Leung, “An optimal solution for channel assignment problem.” IEEE Trans. Computers, vol. C-28. pp. 807–8loT Nov. 1979.
-
(1979)
IEEE Trans. Computers
, vol.28 C
, pp. 807-810
-
-
Gupta, U.1
Lee, D.2
Leung, J.3
-
47
-
-
0016580707
-
Coloring a family of circular arc graphs
-
502
-
A. Tucker. “Coloring a family of circular arc graphs.” SIAM J. Appl. Math., vol. 29. pp. 493. 502 (1975).
-
(1975)
SIAM J. Appl. Math.
, vol.29
, pp. 493
-
-
Tucker, A.1
-
48
-
-
84941480413
-
Scheduling and allocation for pipelined asics
-
Oct.
-
P. Paulin and J. Knight. “Scheduling and allocation for pipelined asics.” in CCVLSI 87, Oct. 1987.
-
(1987)
CCVLSI 87
-
-
Paulin, P.1
Knight, J.2
-
51
-
-
0024138655
-
Splicer: A heuristic approach to connectivity binding
-
B.M. Pangrle. “Splicer: A heuristic approach to connectivity binding.” in 25th DAC, pp. 536–541. 1988.
-
(1988)
25th DAC
, pp. 536-541
-
-
Pangrle, B.M.1
-
52
-
-
0023291444
-
Perspective on BiCMOS VLSI
-
Feb.
-
M. Kubo et al., “Perspective on BiCMOS VLSI.” IEEE J. Solid-State Circuits, vol. 23. Feb. 1988.
-
(1988)
IEEE J. Solid-State Circuits
, vol.23
-
-
Kubo, M.1
|