Simultaneous functional-unit binding and floorplanning

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn , Issue , 1994, Pages 317-321

  Fang, Yung Ming ^a   Wong, D F ^a  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED LOGIC DESIGN; CRITICAL PATH ANALYSIS; INTEGRATED CIRCUIT LAYOUT; RESOURCE ALLOCATION; SYSTEMS ANALYSIS;

DATA FLOW GRAPH; FLOORPLANNING; FUNCTIONAL UNIT BINDING; HIGH LEVEL SYNTHESIS; INTERCONNECTION DELAY;

LOGIC DESIGN;

EID: 0028728368     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (12)