Incorporating Bottom-Up Design into Hardware Synthesis

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 9, Issue 9, 1990, Pages 938-950

  McFarland, Michael C ^a,b   Kowalski, Thaddeus I ^a  

^a LUCENT TECHNOLOGIES   (United States)

^b BOSTON COLLEGE   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DATABASE SYSTEMS; EXPERT SYSTEMS; LOGIC DESIGN; MATHEMATICAL PROGRAMMING, DYNAMIC; SIGNAL PROCESSING--DIGITAL TECHNIQUES;

HARDWARE SYNTHESIS; IC BOTTOM-UP DESIGN;

INTEGRATED CIRCUITS, VLSI;

EID: 0025489298     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.59070     Document Type: Article

References (38)

1. S. W. Director, A. C. Parker, D. P. Siewiorek, and D. E. Thomas, “A design methodology and computer aids for digital VLSI systems,” IEEE Trans. Circuits Syst., vol. CAS-28, pp. 634–645, July 1981.
2. T. J. Kowalski, D. J. Geiger, W. H. Wolf, and W. Fichtner, “The VLSI design automation assistant: From algorithms to silicon,” Design Test Comput., vol. 2, pp. 33–43, Aug. 1985.
3. J. R. Duley and D. L. Dietmeyer, “Translation of a DDL digital system specification to Boolean equations,” IEEE Trans. Computers, vol. C-18, pp. 305–313, 1969.
4. M. C. McFarland, A. C. Parker, and R. Camposano, “Tutorial on high-level synthesis,” in Proc. 25th Design Automation Conf., ACM/ IEEE, June 1988, pp. 330–336.
5. D. E. Thomas, “The design and analysis of an automated design style selector,” Ph.D. dissertation Dept. Elect. Eng., Carnegie-Mellon Univ., Apr. 1977.
6. T. J. Kowalski, An Artificial Intelligence Approach to VLSI Design. Boston, MA: Kluwer Academic, 1985.
7. M. C. McFarland, “Computer-aided partitioning of behavioral hardware descriptions,” in Proc. 20th Design Automation Conf., June 1983, pp. 472–478.
8. C. Mead and L. Conway, Introduction to VLSI Systems. Reading, MA: Addison-Wesley, 1980.
9. H. W. Trickey, “Compiling Pascal programs into silicon,” Ph.D. dissertation, Stanford Univ., July 1985.
10. E. A. Snow, D. P. Siewiorek, and D. E. Thomas, “A technology-relative computer-aided design system: Abstract representations, transformations, and design tradeoffs,” in Proc. 15th Design Automation Conf., ACM/IEEE, 1978, pp. 220–226.
11. C. J. Tseng and D. P. Siewiorek, “Facet: A procedure for the automated synthesis of digital systems,” in Proc. 20th Design Automation Conf, ACM/IEEE, 1983, pp. 490–496.
12. L. J. Hafer and A. C. Parker, “Register-transfer level digital design automation: The allocation process,” in Proc. 15th Design Automation Conf, ACM/IEEE, June 1978, pp. 213–219.
13. D. E. Thomas, C. Y. Hitchcock, III, T. J. Kowalski, J. V. Rajan, and R. Walker, “Automatic data path synthesis,” Comput., vol. 16, no. 12, pp. 59–70, Dec. 1983.
14. G. Zimmermann, “MDS-The Mimola design method,” J. Digital Syst., vol. 4, no. 3, pp. 337–369, 1980.
15. P. Marwedel, “The MIMOLA design system: Tools for the design of digital processors,” in Proc. 21st Design Automation Conf, ACM/ IEEE, June 1984, pp. 587–593.
16. E. D. Lagnese and D. E. Thomas, “Architectural partitioning for system level design,” in Proc. 26th Design Automation Conf. ACM/ IEEE, June 1989, pp. 62–67.
17. D. W. Knapp and A. C. Parker, “A unified representation for design information,” in 7th Int. Symp. on Computer Hardware Description Languages, 1985, pp. 337–353.
18. D. D. Gajski, “The Structure of a silicon compiler, in Proc. Int. Conf. on Circuits and Computers, IEEE, 1982, pp. 272–276.
19. P. G. Paulin and J. P. Knight, “Force-directed scheduling for the behavioral synthesis of ASIC's,” IEEE Trans. Computer-Aided Design, vol. 8, pp. 661–679, June 1989.
20. E. F. Girczyc, “Automatic generation of microsequenced data paths to realize ADA circuit descriptions,” Ph.D. dissertation, Carleton Univ., July 1984.
21. B. M. Pangrle, “Splicer: A heuristic approach to connectivity binding,” in Proc. 25th Design Automation Conf., ACM/IEEE, June 1988, pp. 536–541.
22. J. R. Southard, “MacPitts: An approach to silicon compilation,” Comput., vol. 16, no. 12, pp. 74–82, Dec. 1983.
23. J. V. Rajan, “Automatic synthesis of microprocessors,” Ph.D. dissertation, Carnegie Mellon Univ., Dec. 1988.
24. M. R. Barbacci and D. P. Siewiorek, The Design and Analysis of Instruction Set Processors. New York: McGraw-Hill, 1982.
25. W. H. Wolf, “Fred: A procedural database for VLSI design,” in Proc. 23d Design Automation Conf, ACM/IEEE, June 1986, pp. 744–751.
26. M. C. McFarland, “The VT: A database for automated digital design,” Tech. Rep. DRC-01-4-80, Design Res. Ctr., Carnegie Mellon Univ., Dec. 1978.
27. S. C. Johnson, “Hierarchical clustering schemes,” Psychometrika, vol. 32, no. 3, pp. 241–254, Sept. 1967.
28. S. Davidson, D. Landskov, B. D. Shriver, and P. W. Mallett, “Some experiments in local microcode compaction for horizontal machines,” IEEE Trans. Comput., vol. C-30, pp. 460–477, July 1981.
29. M. C. McFarland, “A fast floorplanning algorithm for architectural evaluation,” in Proc. Int. Conf. on Computer Design, IEEE, Oct. 1989.
30. A. E. Dunlop and B. W. Kernighan, “A procedure for placement of standard-cell VLSI circuits,” IEEE Trans. Computer-Aided Design, vol. CAD-4, pp. 92–98, Jan. 1985.
31. C. Fiduccia and R. M. Mattheyses, “A linear-time heuristic for improving network partitions,” in Proc. 19th Design Automation Conf., IEEE, June 1982, pp. 175-181.
32. B. W. Kernighan and S. Lin, “An efficient heuristic procedure for partitioning graphs,” Bell Syst. Tech. J., vol. 49, 1970.
33. D. LaPotin and S. W. Director, “Mason: A global floorplanning approach to VLSI design,” IEEE Trans. Computer-Aided Design, vol. CAD-5, pp. 477–489, Oct. 1986.
34. G. Zimmerman, “A new area and shape function estimation technique for VLSI layouts,” in Proc. 25th Design Automation Conf., ACM/IEEE, June 1988, pp. 60-65.
35. J. Newkirk and R. Mathews, The VLSI Designer's Library. Reading, MA: Addison-Wesley, 1983.
36. M. R. Barbacci, “Automated exploration of the design space for register transfer (RT) systems,” Ph.D. dissertation, Camegie Mellon Univ., 1973.
37. L. J. Hafer, “Automated data-memory synthesis: A formal method for the specification, analysis, and design of register-transfer level digital logic,” Ph.D. dissertation Dep. Elec. Eng., Carnegie Mellon Univ., June 1981: also in Design Research Center Tech. Rep. DRC-02-05-81.
38. G. W. Leive and D. E. Thomas, “A technology relative logic synthesis and module selection system,” in Proc. 18th Design Automation Conf., ACM/IEEE, 1981, pp. 479-485.