Software transactional memory

Queue

Volumn 6, Issue 5, 2008, Pages 46-58

  Caşcaval, Cǎlin ^a,b   Blundell, Colin ^c   Michael, Maged ^g   Cain, Harold W ^g   Wu, Peng ^g   Chiras, Stefanie ^d   Chatterjee, Siddhartha ^e,f  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b Compilers Team in the PERCS Project ^*

^c UNIVERSITY OF PENNSYLVANIA   (United States)

^d IBM   (United States)

^e Austin Rheumatology Research   (United States)

^f University of Texas at Austin   (United States)

^g NONE

Author keywords

[No Author keywords available]

Indexed keywords

EID: 78651589831     PISSN: 15427730     EISSN: 15427749     Source Type: Journal    
DOI: 10.1145/1454456.1454466     Document Type: Article

References (57)

1. th Annual International Symposium on Computer Architecture (May): 289-300.
2. Larus, J.R., Rajwar, R. 2006. Transactional Memory. Morgan Claypool.
3. Dice, D., Shalev, O., Shavit, N. 2006. Transactional Locking II. DISC (September): 194-208.
4. Harris, T., Fraser, K. 2003. Language support for light-weight transactions. In Proceedings of Object-Oriented Programming, Systems, Languages, and Applications (October): 388-402.
5. nd ACM Symposium on Principles of Distributed Computing (July): 92-101.
6. Intel C++ STM compiler, prototype edition 2.0.; http://softwarecommunity. intel.com/articles/eng/1460.htm/(2008).
7. Marathe, V.J., Spear, M.F., Heriot, C., Acharya, A., Eisenstat, D., Scherer III, W.N., Scott, M.L. 2006. Lowering the overhead of software transactional memory. Technical Report TR 893, Computer Science Department, University of Rochester (March). Condensed version submitted for publication.
8. th ACM Symposium on Principles and Practice of Parallel Programming (March): 187-197.
9. Shavit, N., Touitou, D. 1995. Software Transactional Memory. In Proceedings of the ACM Symposium of Principles of Distributed Computing: 204-213.
10. th Annual International Symposium on Computer Architecture: 23-34.
11. th International Symposium on Computer Architecture: 127-138.
12. st Annual International Symposium on Computer Architecture (June): 102.
13. See reference 1.
14. th Annual International Symposium on Computer Architecture: 69-80.
15. th Annual International Symposium on High Performance Computer Architecture (February).
16. th International Symposium on High-Performance Computer Architecture (February).
17. th Annual International Symposium on Computer Architecture: 237-238.
18. Tremblay, M. Chaudhry, S. 2008. A third-generation 65nm 16-core 32-thread plus 32-scout-thread CMT. In Proceedings of the IEEE International Solid-State Circuits Conference (February).
19. th International Symposium on Computer Architecture: 115-126.
20. th International Conference on Architectural Support for Programming Languages and Operating Systems (October).
21. th Annual International Symposium on Microarchitecture (December): 185-196.
22. th Annual International Symposium on Computer Architecture: 104-115.
23. STAMP benchmark suite. 2007. http://stamp.stanford.edu/.
24. The Lonestar benchmark suite. 2008. http://iss.ices.utexas.edu/lonestar/.
25. (IBM) XL C/C++ for Transactional Memory for AIX. 2008. www.alphaworks.ibm.com/tech/xlcstm/.
26. See reference 6.
27. See reference 3.
28. Blundell, C., Lewis, C., and Martin, M.M.K. 2006. Subtleties of transactional memory atomicity semantics. IEEE TCCA Computer Architecture Letters 5(2).
29. Kulkarni, M., Pingali, K., Walter, B., Ramanarayanan, G., Bala, K., Chew, P.L. 2007. Optimistic parallelism requires abstractions. In Proceedings of the PLDI: 211-222.
30. See reference 14.
31. See reference 23.
32. See reference 25.
33. Wu, P., Michael, M.M., von Praun, C., Nakaike, T., Bordawekar, R., Cain, H.W., Cascaval, C., Chatterjee, S., Chiras, S., Hou, R., Mergen, M., Shen, X., Spear, M.F., Wang, H.Y., Wang, K. 2008. Compiler and run-time techniques for software transactional memory optimization. To appear in Concurrency and Computation: Practice and Experience.
34. See reference 6.
35. See reference 3.
36. th Annual Symposium on Parallelism in Algorithms and Architectures.
37. See reference 36.
38. See reference 25.
39. Shpeisman, T., Menon, V., Adl-Tabatabai, A-R., Balensiefer, S., Grossman, D., Hudson, R., Moore, K.F., Saha, B. 2007. Enforcing isolation and ordering in STM. In Proceedings of the Programming Language Design and Implementation Conference: 78-88.
40. Harris, T., Plesko, M., Shinnar, A., Tarditi, D. 2003. Optimizing memory transactions. In Proceedings of the Programming Language Design and Implementation Conference: 388-402.
41. See reference 39.
42. See reference 40.
43. th Annual Symposium on Parallelism in Algorithms and Architectures: 326-335.
44. th ACM Symposium on Principles of Distributed Computing: 204-213.
45. See reference 3.
46. See reference 5.
47. See reference 4.
48. See reference 7.
49. th ACM Symposium on Parallelism in Algorithms and Architectures (June).
50. th International Conference on Parallel Architecture and Compilation Techniques: 365-375.
51. th ACM Symposium on Parallelism in Algorithms and Architectures: 275-284.
52. Felber, P., Fetzer, C., Mueller, U., Riegel, T., Suesskraut, M., Sturzrehm, H. 2007. Transactifying applications using an open compiler framework. In Proceedings of the ACM SIGPLAN Workshop on Transactional Computing (August).
53. See reference 50.
54. Wang, C. Chein, W-Y, Wu, Y., Saha, B., Adl-Tabatabai, A.R. 2007. Code generation and optimization for transactional memory constructs in an unmanaged language. In Proceedings of International Symposium on Code Generation and Optimization: 34-48.
55. See reference 36.
56. See reference 6.
57. See reference 8.