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Volumn , Issue , 2006, Pages 336-346

Hybrid transactional memory

Author keywords

Transactional memory

Indexed keywords

PROGRAMMERS; SOFTWARE LIBRARY; TRANSACTIONAL MEMORY;

EID: 34547403150     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1168857.1168900     Document Type: Conference Paper
Times cited : (189)

References (33)
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    • C. S. Ananian, R. Asanovic, B. C. Ruszmaul, C. E. Leiserson, and S. Lie. Unbounded transactional memory. In Proc. 11th International Symposium on High-Performance Computer Architecture, pages 316-327, Feb. 2005.
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    • Lie, S.1
  • 20
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    • Hybrid hardware/software transactional memory
    • Apr
    • M. Moir. Hybrid hardware/software transactional memory. Slides for Chicago Workshop on Transactional Systems, Apr. 2005. http://www.cs.wisc. edurrajwar/tm-workshop/TALKS/moir.pdf.
    • (2005) Slides for Chicago Workshop on Transactional Systems
    • Moir, M.1
  • 23
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    • Thread-level transactional memory
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    • K. E. Moore, M. D. Hill, and D. A. Wood. Thread-level transactional memory. Technical Report: CS-TR-2005-1524, Dept. of Computer Sciences, University of Wisconsin, Mar. 2005.
    • (2005)
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.