Zero-level packaging of MEMS in standard CMOS technology

Journal of Micromechanics and Microengineering

Volumn 20, Issue 6, 2010, Pages

  Marigo E ^a   Lopez, J L ^a   Murillo, G ^a   Torres, F ^a   Giner, J ^a   Uranga, A ^a   Abadal, G ^a   Esteve, J ^b   Barniol, N ^a  

^a UNIVERSITAT AUTÒNOMA DE BARCELONA   (Spain)

^b INSTITUTO DE MICROELECTRÓNICA DE BARCELONA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS CHIPS; CMOS TECHNOLOGY; ELECTRICAL FREQUENCY; ELECTRICAL MEASUREMENT; GLOBAL PACKAGING; MEMS RESONATORS; MEMSDEVICES; METAL DEPOSITION; METAL LAYER; NOVEL TECHNIQUES; ON CHIPS; PHYSICAL CHARACTERIZATION; POLYSILICON RESONATORS; POST PROCESSING; STANDARD CMOS TECHNOLOGY; VACUUM SEALS; WET-ETCHING PROCESS; ZERO-LEVEL PACKAGING;

CHIP SCALE PACKAGES; CMOS INTEGRATED CIRCUITS; FREQUENCY RESPONSE; MICROELECTROMECHANICAL DEVICES; POLYSILICON; RESONATORS; WET ETCHING;

PACKAGING;

EID: 78650924295     PISSN: 09601317     EISSN: 13616439     Source Type: Journal    
DOI: 10.1088/0960-1317/20/6/064009     Document Type: Article

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