Through Silicon Vias technology for CMOS image sensors packaging: Presentation of technology and electrical results

10th Electronics Packaging Technology Conference, EPTC 2008

Volumn , Issue , 2008, Pages 35-44

  Henry, D ^a   Charbonnier, J ^a   Chausse, P ^a   Jacquet, F ^a   Aventurier, B ^a   Brunet Manquat, C ^a   Lapras, V ^a   Anciant, R ^a   Sillon, N ^a   Dunne, B ^b   Hotellier, N ^b   Michailos, J ^b  

^a CEA LETI   (France)

^b STMICROELECTRONICS   (France)

Author keywords

Advanced packaging; CMOS image sensors (CIS); Design rules; Electrical measurements; Through Silicon Vias (TSV); Wafer level technologies

Indexed keywords

ALIGNMENT; CHARACTERIZATION; CHIP SCALE PACKAGES; DESIGN; DIGITAL CAMERAS; DIGITAL IMAGE STORAGE; ELECTRIC CONDUCTIVITY; ELECTRIC VARIABLES MEASUREMENT; ELECTRONIC EQUIPMENT MANUFACTURE; GLASS BONDING; INTERCONNECTION NETWORKS; IONIZATION OF GASES; NONMETALS; PACKAGING; PIXELS; SEMICONDUCTING SILICON COMPOUNDS; SILICON WAFERS; TECHNOLOGY; WAFER BONDING;

ADVANCED PACKAGING; CMOS IMAGE SENSORS (CIS); DESIGN RULES; ELECTRICAL MEASUREMENTS; THROUGH SILICON VIAS (TSV); WAFER LEVEL TECHNOLOGIES;

IMAGE SENSORS;

EID: 63049135179     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPTC.2008.4763409     Document Type: Conference Paper

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