Fine grain thermal modeling of 3D stacked structures

15th International Workshop on Thermal Investigations of ICs and Systems, THERMINIC 2009

Volumn , Issue , 2009, Pages 45-49

  Oprins, H ^a   Cupak, M ^a   Van Der Plas, G ^a   Marchal, P ^a   Vandevelde, B ^a   Srinivasan, A ^b   Cheng, E ^b  

^a IMEC   (Belgium)

^b Gradient Design Automation Inc   (United States)

Author keywords

3D stacked ICs; Design layout; Thermal aware design; Thermal modeling

Indexed keywords

3D INTERCONNECT; 3D STACKING; BACK END OF LINES; BGA PACKAGE; DESIGN LAYOUT; ELECTRICAL DESIGN; ELECTRONIC SYSTEMS; FINE GRAINS; KEY TECHNOLOGIES; MULTILAYER INTERCONNECTIONS; NUMERICAL TECHNIQUES; PERFORMANCE ENHANCEMENTS; STACKED DIE; STACKED DIE PACKAGES; STACKED STRUCTURE; THERMAL ANALYSIS; THERMAL MODELING; THERMAL SPREADING; THERMAL-AWARE DESIGN;

DIES; ELECTRONICS PACKAGING; THERMOANALYSIS; THREE DIMENSIONAL;

STRUCTURAL DESIGN;

EID: 71749118577     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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