Total dose effects on the performance of irradiated capacitorless MSDRAM cells

IEEE Transactions on Nuclear Science

Volumn 57, Issue 6 PART 1, 2010, Pages 3054-3059

  El Mamouni, Farah ^a   Bawedin, Maryline ^b   Zhang, Enxia X ^a   Schrimpf, Ronald D ^a   Fleetwood, Daniel M ^a   Cristoloveanu, Sorin ^b  

^a VANDERBILT UNIVERSITY   (United States)

^b IMEP LAHC   (France)

Author keywords

1T DRAM; band to band tunneling (BTBT); body potential; buried oxide (BOX); fully depleted (FD); metastable dip (MSD) effect; MSDRAM; retention time; silicon on insulator (SOI); total ionizing dose (TID)

Indexed keywords

1T-DRAM; BAND TO BAND TUNNELING; BODY POTENTIAL; BURIED OXIDES; FULLY DEPLETED; METASTABLE DIP (MSD) EFFECT; MSDRAM; RETENTION TIME; SILICON-ON-INSULATOR (SOI); TOTAL IONIZING DOSE;

CAPACITORS; DRAIN CURRENT; DYNAMIC RANDOM ACCESS STORAGE; FINITE DIFFERENCE METHOD; SILICON COMPOUNDS; SILICON ON INSULATOR TECHNOLOGY; SILICON OXIDES;

IONIZING RADIATION;

EID: 78650377459     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2010.2077310     Document Type: Conference Paper

References (20)

1. P. Fazan, S. Okhonin, M. Nagoga, J. M. Sallese, L. Portman, R. Ferrant, M. Kayal, M. Pastre, and M. Declerq, "Capacitor-less 1-transistor DRAM," in Proc. IEEE Int. SOI Conf., Williamsburg, VA, Oct. 7-10, 2002, pp. 10-13.
2. S. Okhonin, M. Nagoga, J. M. Sallese, and P. Fazan, "A capacitor-less 1T-DRAM cell," IEEE Electron Device Lett., vol. 23, no. 2, pp. 85-87, Feb. 2002.
3. E. Yoshida and T. Tanaka, "A design of a capacitor-less 1T-DRAM cell using gate-induced drain leakage (GIDL) current for low-power and high-speed em-bedded memory," IEDM Tech. Dig., pp. 37.6.1-37.6.4, 2003.
4. T. Tanaka, E. Yoshida, and T. Miyashita, "Scalability study on a capacitor-less 1T-DRAM: From single-gate PD-SOI to double-gate FinDRAM," IEDM Tech. Dig., pp. 919-922, 2004.
5. M. Bawedin, S. Cristoloveanu, and D. Flandre, "A capacitor-less 1T-DRAM on SOI based on dynamic coupling and double-gate operation," IEEE Electron Device Lett., vol. 29, no. 7, pp. 795-798, Jul. 2008.
6. S. Okhonin, M. Nagoga, J. M. Sallese, and P. Fazan, "A SOI capacitor- less 1T-DRAM concept," in Proc. IEEE Int. SOI Conf., 2001, pp. 153-154.
7. M. Bawedin, S. Cristoloveanu, and D. Flandre, "Unusual floating body effect in fully depleted MOSFETs," in Proc. IEEE Int. SOI Conf., 2004, pp. 151-152.
8. M. Bawedin, S. Cristoloveanu, J. G. Yun, and D. Flandre, "A new memory effect (MSD) in fully depleted SOI MOSFETs," Solid-State Electron., vol. 49, pp. 1547-1555, 2005.
9. M. Bawedin, S. Cristoloveanu, and D. Flandre, "Unusual gate current transient behavior in SOI MOSFETs," in Proc. IEEE Int. SOI Conf., 2005, pp. 67-69.
10. A. Hubert, S. Cristoloveanu, M. Bawedin, and T. Ernst, "Scalability of MSD memory effect," in Proc. Ultimate Integration of Silicon Conf., 2009, pp. 139-142.
11. V. Ferlet-Cavrois, T. Colladant, P. Paillet, J. L. Leray,O.Musseau, J. R. Schwank, M. R. Shaneyfelt, J. L. Pelloie, and J. du Port de Poncharra, "Worst case bias during the total dose irradiation of SOI transistors," IEEE Trans. Nucl. Sci., vol. 47, no. 6, pp. 2183-2188, Dec. 2000.
12. V. Ferlet-Cavrois, S. Quoizola, O. Musseau, O. Flament, J. L. Leray, J. L. Pelloie, C. Raynaud, and O. Faynot, "Total dose induced latch in short channel NMOS/SOI transistors," IEEE Trans. Nucl. Sci., vol. 45, no. 6, pp. 2458-2466, Dec. 1998.
13. F. El-Mamouni, S. K. Dixit, R. D. Schrimpf, P. C. Adell, I. S. Esqueda, M. L. McLain, H. J. Barnaby, S. Cristoloveanu, and W. Xiong, "Gatelength and drain-bias dependence of band-to-band tunneling-induced drain leakage in irradiated fully depleted SOI devices," IEEE Trans. Nucl. Sci., vol. 55, no. 6, pt. 1, pp. 3259-3264, Dec. 2008.
14. M. Bawedin, S. Cristoloveanu, D. Flandre, and F. Udera, "Dynamic body potential variation in FD SOI MOSFETs operated in deep nonequilibrium regime: Model and application," Solid State Electron., vol. 54, pp. 104-114, 2010.
15. J. R. Schwank, D. M. Fleetwood, H. D. Xiong, M. R. Shaneyfelt, and B. L. Draper, "Generation of metastable electron traps in the near interfacial region of SOI buried oxides by ion implantation and their effect on device properties," Microelectron. Eng., vol. 72, pp. 362-366, 2004.
16. B. J. Mrstik, H. L. Hughes, P. J. McMarr, R. K. Lawrence, D. I. Ma, I. P. Isaaccson, and R. A. Walker, "Hole and electron trapping in ion implanted thermal oxides and SIMOX," IEEE Trans. Nucl. Sci., vol. 47, no. 6, pt. 3, pp. 2189-2195, 2000.
17. M. Bawedin, "Transient floating-body effects for memory applications in fully-depleted SOI MOSFETs," Ph.D. dissertation, Univ. Katholieke Louvain, Louvain-de-la-Nueve, Belgium, 2007.
18. P. C. Adell, H. J. Barnaby, R. D. Schrimpf, and B. Vermeire, "Band-toband tunneling (BBT) induced leakeage current enhancement in irradiated fully depleted SOI devices," IEEE Trans. Nucl. Sci., vol. 54, no. 6, pp. 2174-2180, Dec. 2007.
19. M. Bawedin, S. Cristoloveanu, D. Flandre, C. Renaux, and A. Crahay, "Double-gate floating-body memory device," Patent PCT-EP2009-050031, Jan. 5, 2009.
20. E. X. Zhang, D. M. Fleetwood, F. E. Mamouni, M. L. Alles, R. D. Schrimpf, W. Xiong, and S. Cristoloveanu, "Effects of fin width on memory windows in FinFET ZRAMs," Solid State Electron., vol. 54, pp. 1155-1159, 2010.