Worst-case bias during total dose irradiation of SOI transistors

IEEE Transactions on Nuclear Science

Volumn 47, Issue 6 III, 2000, Pages 2183-2188

  Ferlet Cavrois, V ^a,b   Colladant, T ^b   Paillet, P ^a,b   Leray, J L ^a,b   Musseau, O ^a,b   Schwank, J R ^a,c   Shaneyfelt, M R ^a,c   Pelloie, J L ^d   Du Port De Poncharra, J ^d  

^a IEEE   (France)

^b CEA DIF   (France)

^c SANDIA NATIONAL LABORATORIES   (United States)

^d CEA LETI   (France)

Author keywords

[No Author keywords available]

Indexed keywords

CHARGE TRAPPING; THRESHOLD VOLTAGE SHIFT; TOTAL DOSE IRRADIATION; WORST-CASE BIAS;

COMPUTER SIMULATION; CORRELATION METHODS; IRRADIATION; OXIDES; THRESHOLD VOLTAGE; TRANSISTORS;

SILICON ON INSULATOR TECHNOLOGY;

EID: 0034452278     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/23.903751     Document Type: Conference Paper

References (18)

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