Scalability study on a capacitorless 1T-DRAM: From single-gate PD-SOI to double-gate FinDRAM

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2004, Pages 919-922

  Tanaka, T ^a   Yoshida, E ^a   Miyashita, T ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITORS; COMPUTATIONAL COMPLEXITY; DYNAMIC RANDOM ACCESS STORAGE; EMBEDDED SYSTEMS; FIELD EFFECT TRANSISTORS; LEAKAGE CURRENTS; SCALABILITY;

BAND-TO-BAND TUNNELING; DOUBLE-GATE FINDRAM; GATE-INDUCED DRAIN LEAKAGE (GIDL); RETENTION TIME;

GATES (TRANSISTOR); DYNAMIC RANDOM ACCESS STORAGE;

CAPACITOR-LESS; DOUBLE-GATE; DOUBLE-GATE FINDRAM; EMBEDDED MEMORY; FULLY DEPLETED; GATE-LENGTH; POWER; RETENTION TIME; SINGLE GATES; STRUCTURAL COMPLEXITY;

EID: 21644432584     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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