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Volumn 57, Issue 6 PART 1, 2010, Pages 3575-3581

Selection of well contact densities for latchup-immune minimal-area ics

Author keywords

Design rule; external resistor; hardening by design; latchup test structure; single event latchup

Indexed keywords

DESIGN RULES; EXTERNAL RESISTOR; HARDENING BY DESIGN; LATCH-UPS; SINGLE EVENT LATCH-UP;

EID: 78650339898     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2010.2082562     Document Type: Conference Paper
Times cited : (23)

References (20)
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  • 2
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    • Mavis, D.G.1    Alexander, D.R.2
  • 4
    • 48349118284 scopus 로고    scopus 로고
    • The effects of scaling and well and substrate contact placement on single event latchup in bulk CMOS technology
    • J. M. Hutson, R. D. Schrimpf, and L. W. Massengill, "The effects of scaling and well and substrate contact placement on single event latchup in bulk CMOS technology," in Proc. RADECS, 2005, pp. PC24-1-PC24-5.
    • (2005) Proc. RADECS
    • Hutson, J.M.1    Schrimpf, R.D.2    Massengill, L.W.3
  • 5
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    • LET spectra of proton energy levels from 50 to 500 MeV and their effectiveness for single event effects characterization of microelectronics
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    • D. Hiemstra and E. Blackmore, "LET spectra of proton energy levels from 50 to 500 MeV and their effectiveness for single event effects characterization of microelectronics," IEEE Trans. Nucl. Sci., vol. 50, no. 6, pp. 2245-2250, Dec. 2003.
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  • 13
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    • IC latchup test
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    • The influence of VLSI technology evolution on radiation-induced latchup in space systems
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    • A. H. Johnston, "The influence of VLSI technology evolution on radiation-induced latchup in space systems," IEEE Trans. Nucl. Sci., vol. 43, no. 2, pp. 505-521, Apr. 1996.
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  • 20
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    • Simultaneous single event charge sharing and parasitic bipolar conduction in a highly-scaled SRAM design
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.