The effects of scaling and well and substrate contact placement on single event latchup in bulk CMOS technology

Proceedings of the European Conference on Radiation and its Effects on Components and Systems, RADECS

Volumn , Issue , 2005, Pages

  Hutson, John M ^a,b   Schrimpf, R D ^a,b   Massengill, L M ^a,b  

^a IEEE

^b VANDERBILT UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BULK CMOS; EUROPEAN; SINGLE EVENT LATCH UP (SEL); SUPPLY VOLTAGES; TCAD SIMULATIONS;

RADIATION EFFECTS;

EID: 48349118284     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RADECS.2005.4365577     Document Type: Conference Paper

References (11)

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9. Y. Moreau, H. de La Rochette, G. Bruguier, J. Gasiot, F. Pelanchon, C. Sudre, and R. Ecoffet, "The Latchup Risk of CMOS-Technology in Space", IEEE Trans. Nuc. Sci., vol. 40, no. 6, Dec. 1993, pp. 1831-1837.
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