A 1 GHz ADPLL with a 1.25 ps minimum-resolution sub-exponent TDC in 0.18 μm CMOS

IEEE Journal of Solid-State Circuits

Volumn 45, Issue 12, 2010, Pages 2874-2881

  Lee, Seon Kyoo ^a   Seo, Young Hun ^a   Park, Hong June ^a   Sim, Jae Yoon ^a  

^a Pohang University of Science and Technology (POSTECH)   (South Korea)

Author keywords

All digital PLL; PLL; time amplifier; time to digital converter

Indexed keywords

ALL-DIGITAL PLL; MAXIMUM OPERATING FREQUENCY; PLL; POWER CONSUMPTION; SELF CALIBRATION; TIME AMPLIFIER; TIME TO DIGITAL CONVERTERS; TIME-DIFFERENCES;

JITTER; MICROPROCESSOR CHIPS;

FREQUENCY CONVERTERS;

EID: 78650052925     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2010.2077110     Document Type: Conference Paper

References (16)

1. V. Kratyuk et al, "A design procedure for all-digital phase-locked loops based on a charge-pump phase-locked-loop analogy", IEEE Trans. Circuits Syst. II, vol. 54, no. 3, Mar. 2007.
2. T. Olsson and P. Nilsson, "A digitally controlled PLL for SoC applications", IEEE J. Solid-State Circuits, vol. 39, pp. 751-760, May 2004.
3. R. B. Staszewski, "Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS process", IEEE Trans. Circuits Syst. II, vol. 50, pp. 815-828, Nov. 2003.
4. J. A. Tierno et al., "A wide power supply range, wide tuning range, all static CMOS all digital PLL in 65 nm SOI", IEEE J. Solid-State Cir., vol. 43, no. 1, pp. 42-51, Jan. 2008.
5. V. Kratyuk, "A digital PLL with a stochastic time-to-digital converter", in Proc. Symp. VLSI Circuits, Jun. 2006, pp. 38-39.
6. S.-Y. Yang et al., "A 7.1 mW 10 GHz all-digital frequency synthesizer with dynamically reconfigurable digital loop filter in 90 nm CMOS", in IEEE Int. Solid-State Circuits Conf. Dig., Feb. 2009, pp. 90-91.
7. R. B. Staszewski et al., "All-digital PLL and transmitter for mobile phones", IEEE J. Solid-State Circuits, vol. 40, pp. 2469-2482, Dec. 2005.
8. R. B. Staszewski et al, "1.3 V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS", IEEE Trans. Circuits Syst. II, vol. 53, no. 3, pp. 220-224, Mar. 2006.
9. P. Dudek et al., "A high-resolution CMOS time-to-digital converter utilizing a vernier delay line", IEEE J. Solid-State Cir., vol. 35, no. 2, pp. 240-247, Feb. 2000.
10. J. Yu et al, "A 12-bit vernier ring time-to-digital converter in 0.13 μm CMOS technology", in IEEE Symp. VLSI Circuits Dig., Jun. 2009, pp. 232-233.
11. J. Lin et al, "A PVT tolerant 0.18 MHz to 600 MHz self-calibrated digital PLL in 90 nm CMOS process", in IEEE Int. Solid-State Circuits Conf., Feb. 2004, pp. 488-489.
12. M. Lee et al., "A 9 b, 1.25 ps resolution coarse-fine time-to-digital converter in 90 nm CMOS that amplifies a time residue", in IEEE Symp. VLSI Circuits Dig., Jun. 2007, pp. 168-169.
13. M. Z. Straayer et al., "An efficient high-resolution 11-bit noise-shaping multipath gated ring oscillator TDC", in IEEE Symp. VLSI Circuits Dig., Jun. 2008, pp. 82-83.
14. A. M. Abas et al, "Time difference amplifier", IEE Electronics Lett, vol. 38, no. 23, pp. 1437-1438, Nov. 2002.
15. S.-K. Lee et al, "A 1 GHz ADPLL with a 1.25 ps minimum-resolution sub-exponent TDC in 0.18 μm CMOS", in IEEE Int. Solid-State Circuits Conf. Dig., Feb. 2010, pp. 482-483.
16. D.-H. Oh et al, "A 2.8 Gb/s all-digital CDR with a 10 b monotonic DCO", in IEEE Int. Solid-State Circuits Conf. Dig., Feb. 2007, pp. 222-223.