A 2.8GD/S all-digital CDR with a 10b monotonic PCO

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2007, Pages 222-224

  Oh, Do Hwan ^a   Kim, Deok Soo ^a   Kim, Suhwan ^a   Jeong, Deog Kyoon ^a   Kim, Wonchan ^a  

^a Seoul National University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; FREQUENCY BANDS; JITTER; TUNING;

FREQUENCY TUNING; QUANTIZATION EFFECT;

DIGITAL CIRCUITS;

EID: 34548828224     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2007.373374     Document Type: Conference Paper

References (5)

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2. B.J. Lee, M. Hwang, J. Kim, et al., "A Quad 3.125Gb/s Transceiver Cell with All-Digital Data Recovery Circuits," Symp. VLSI Circuits Dig., pp. 384-387, Jun., 2005.
3. T. Olsson and P. Nilsson, "A Digitally Controlled PLL for SoC Applications," IEEE J. Solid-State Circuits, vol.39, pp. 751-760, May, 2004.
4. J. A. Shoeff, "An Inherently Monotonic 12 bit DAC," IEEE J. Solid-State Circuits, vol. SC-14, no. 6, pp. 904-911, Dec., 1979.
5. A. Maxim, B. Scott, E.M. Schneider, et al., "A Low-Jitter 125-1250 MHz Process-Independent and Ripple-Poleless 0.18μm CMOS PLL Based on a Sample-Reset Loop Filter," IEEE J. Solid-State Circuits, pp. 1673-1683, Nov., 2001.