A design procedure for all-digital phase-locked loops based on a charge-pump phase-locked-loop analogy

IEEE Transactions on Circuits and Systems II: Express Briefs

Volumn 54, Issue 3, 2007, Pages 247-251

  Kratyuk, Volodymyr ^a   Hanumolu, Pavan Kumar ^a   Moon, Un Ku ^a   Mayaram, Kartikeya ^a  

^a 1148 Kelley Engineering Center Corvallis   (United States)

Author keywords

All digital phase locked loop (PLL); bilinear transform; digital loop filter; digitally controlled oscillator

Indexed keywords

DIGITAL FILTERS; FREQUENCY RESPONSE; FREQUENCY STABILITY; MATHEMATICAL TRANSFORMATIONS; OSCILLATORS (ELECTRONIC);

ALL-DIGITAL PHASE-LOCKED LOOPS; BILINEAR TRANSFORM; DIGITAL LOOP FILTER; DIGITALLY CONTROLLED OSCILLATOR;

PHASE LOCKED LOOPS;

EID: 34147133722     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2006.889443     Document Type: Article

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