Effects of gate-bias stress on ZnO thin-film transistors

Journal of the Society for Information Display

Volumn 18, Issue 10, 2010, Pages 802-806

  Su, Liang Yu ^a   Lin, Hsin Ying ^a   Wang, Sung Li ^a   Yeh, Yung Hui ^b   Cheng, Chun Cheng ^b   Peng, Lung Han ^a   Huang, Jian Jang ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

^b INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

Author keywords

Bias stress; Stability; Thin film transistors (TFTs); ZnO

Indexed keywords

A-THERMAL; ANNEALING CONDITION; BIAS STRESS; CHANNEL CONDUCTANCE; DEVICE STABILITY; EFFECTIVE ENERGY; GATE-BIAS STRESS; GLASS SUBSTRATES; INTERFACE QUALITY; POSTGROWTH ANNEALING; STABILITY ISSUES; THIN-FILM TRANSISTORS (TFTS); TIME CONSTANTS; TRAP STATE; ZNO;

ANNEALING; STABILITY; SUBSTRATES; ZINC OXIDE;

THIN FILM TRANSISTORS;

EID: 77958193683     PISSN: 10710922     EISSN: None     Source Type: Journal    
DOI: 10.1889/JSID18.10.802     Document Type: Article

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