Adaptive pipeline structures for speculation control

Proceedings - International Symposium on Asynchronous Circuits and Systems

Volumn , Issue , 2003, Pages 46-55

  Efthymiou, Aristides ^a   Garside, Jim D ^a  

^a UNIVERSITY OF MANCHESTER   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

PIPELINES;

AND SPLITS; ASYNCHRONOUS PIPELINE; DYNAMIC ADAPTATIONS; ENERGY WASTES; PIPELINE DEPTH; PIPELINE STAGES; PIPELINE STRUCTURE; PIPELINED SYSTEMS; RUNTIMES; SPECULATION CONTROLS;

ENERGY DISSIPATION;

EID: 77957965194     PISSN: 26431394     EISSN: 26431483     Source Type: Conference Proceeding    
DOI: 10.1109/ASYNC.2003.1199165     Document Type: Conference Paper

References (11)

1. L. Benini, M. Favalli, and B. Riccò. Analysis of hazard contribution to power dissipation in CMOS IC's. In Proceedings of the International Workshop on Low Power Design, pages 27-32, May 1994.
2. E. Boemo, S. Lopez-Buedo, C. Santos Perez, J. Jauregui, and J. Meneses. Logic depth and power consumption: A comparative study between standard cells and FPGAs. In Proceedings of the XIII Design of Circuits and Integrated Systems (DCIS) Conference, Nov. 1998.
3. J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno, and A. Yakovlev. Petrify: a tool for manipulating concurrent specifications and synthesis of asynchronous controllers. IEICE Transactions on Information and Systems, E80-D(3):315-325, Mar. 1997.
4. A. Efthymiou and J. D. Garside. Adaptive pipeline depth control for processor power-management. In Proceedings of International Conference on Computer Design, pages 454-457. IEEE Computer Society Press, Sept. 2002.
5. J. D. Garside, S. B. Furber, and S. Chung. AMULET3 revealed. In Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 51-59, Apr. 1999.
6. J. Hennessy and D. Patterson. Computer Architecture: A Quantitative Approach. Morgan Kaufmann, second edition, 1996.
7. H. M. Jacobson, P. N. Kudva, P. Bose, P. W. Cook, S. E. Schuster, E. G. Mercer, and C. J. Myers. Synchronous interlocked pipelines. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 3-12. IEEE Computer Society Press, Apr. 2002.
8. M. Lewis, J. D. Garside, and L. Brackenbury. Reconfigurable latch controllers for low power asynchronous circuits. In Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 27-35, Apr. 1999.
9. P. Riocreux, M. Lewis, and L. Brackenbury. Power reduction in self-timed circuits using early-open latch controllers. IEE Electronics Letters, 36(2):115-116, Jan. 2000.
10. J. Sparsø and S. B. Furber, editors. Principles of Asynchronous Circuit Design: A Systems Perspective. Kluwer Academic Publishers, 2001.
11. I.E. Sutherland. Micropipelines. Communications of the ACM, 32(6):720-738, June 1989.