Fully depleted strained silicon-on-insulator p-MOSFETs with recessed and embedded silicongermanium source/drain

IEEE Electron Device Letters

Volumn 31, Issue 10, 2010, Pages 1074-1076

  Baudot, Sophie ^a   Andrieu, Francois ^a   Weber, Olivier ^a   Perreau, Pierre ^a   Damlencourt, Jean Franois ^a   Barnola, Sebastien ^a   Salvetat, Thierry ^a   Tosti, Lucie ^a   Brevard, Laurent ^a   Lafond, Dominique ^a   Eymery, Joel ^a   Faynot, Olivier ^a  

^a CEA GRENOBLE   (France)

Author keywords

MOSFETs; silicon on insulator (SOI) technology; silicongermanium (SiGe); strain

Indexed keywords

DRIVE CURRENT ENHANCEMENT; FULLY DEPLETED; GATE LENGTH; GATE VOLTAGES; LOW FIELD MOBILITY; MOBILITY ENHANCEMENT; MOSFETS; P-MOSFETS; RESISTANCE REDUCTION; SERIES RESISTANCES; SILICON GERMANIUM; SILICON-ON-INSULATOR (SOI) TECHNOLOGY; SILICON-ON-INSULATORS; SOI PMOS; STRAINED SILICON-ON-INSULATOR; STRAINED-SOI;

MOSFET DEVICES; SEMICONDUCTING SILICON COMPOUNDS; SILICON; SILICON ALLOYS;

SILICON ON INSULATOR TECHNOLOGY;

EID: 77957588628     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2010.2057500     Document Type: Article

References (13)

1. 2 gate stack," in IEDM Tech. Dig., 2007, pp. 61-64.
2. O. Weber, O. Faynot, F. Andrieu, C. Buj-Dufournet, F. Allain, P. Scheiblin, J. Foucher, N. Daval, D. Lafond, L. Tosti, L. Brevard, O. Rozeau, C. Fenouillet-Beranger, M. Marin, F. Boeuf, D. Delprat, K. Bourdelle, B.-Y. Nguyen, and S. Deleonibus, "High immunity to threshold voltage variability in undoped ultra-thin FDSOI MOSFETs and its physical understanding," in IEDM Tech. Dig., 2008, pp. 245-248.
3. S. Baudot, J. Eymery, F. Andrieu, V. Vidal, F. Allain, L. Brévard, and O. Faynot, "Width and orientation effects in strained FDSOI MOSFETs: Strain and device characterization," in Proc. ESSDERC, 2009, pp. 391-394.
4. S. Pidin, T. Mori, K. Inoue, S. Fukuta, N. Itoh, E. Mutoh, K. Ohkoshi, R. Nakamura, K. Kobayashi, K. Kawamura, T. Saiki, S. Fukuyama, S. Satoh, M. Kase, and K. Hashimoto, "A novel strain enhanced CMOS architecture using selectively deposited high tensile and high compressive silicon nitride films," in IEDM Tech. Dig., 2004, pp. 213-216.
5. T. Mizuno, N. Sugiyama, T. Tezuka, Y. Moriyama, S. Nakaharai, and S. Takagi, "(110)-surface strained-SOI CMOS devices," IEEE Trans. Electron Devices, vol.52, no.3, pp. 367-374, Mar. 2005.
6. K.-W. Ang, K.-J. Chui, V. Bliznetsov, C.-H. Tung, A. Du, N. Balasubramanian, G. Samudra, M.-F. Li, and Y.-C. Yeo, "Lattice strain analysis of transistor structures with silicon-germanium and silicon-carbon source/drain stressors," Appl. Phys. Lett., vol.86, no.9, pp. 093 102-1-093 102-3, Feb. 2005.
7. Y.-C. Yeo and J. Sun, "Finite-element study of strain distribution in transistor with silicon-germanium source and drain regions," Appl. Phys. Lett., vol.86, no.2, pp. 023103-1-023103-3, Jan. 2005.
8. K.-W. Ang, K.-J. Chui, A. Madan, L.-Y. Wong, C.-H. Tung, N. Balasubramanian, M.-F. Li, G.-S. Samudra, and Y.-C. Yeo, "Strained thin-body p-MOSFET with condensed silicon-germanium source/drain for enhanced drive current performance," IEEE Electron Device Lett., vol.28, no.6, pp. 509-512, Jun. 2007.
9. K. Cheng, A. Khakifirooz, P. Kulkarni, S. Ponoth, J. Kuss, D. Shahrjerdi, L.-F. Edge, A. Kimball, S. Kanakasabapathy, K. Xiu, S. Schmitz, A. Reznicek, T. Adam, H. He, N. Loubet, S. Holmes, S. Mehta, D. Yang, A. Upham, S.-C. Seo, J. L. Herman, R. Johnson, Y. Zhu, P. Jamison, B. S. Haran, Z. Zhu, L. H. Vanamurth, S. Fan, D. Horak, H. Bu, P. J. Oldiges, D. K. Sadana, P. Kozlowski, D. McHerron, J. ONeill, and B. Doris, "Extremely thin SOI (ETSOI) CMOS with record low variability for low power system-on-chip applications," in IEDM Tech. Dig., 2009, pp. 49-52.
10. A. V.-Y. Thean, D. Zhang, V. Vartanian, V. Adams, J. Conner, M. Canonico, H. Desjardin, P. Grudowski, B. Gu, Z.-H. Shi, S. Murphy, G. Spencer, S. Filipiak, D. Goedeke, X.-D. Wang, B. Goolsby, V. Dhandapani, L. Prabhu, S. Backer, L.-B. La, D. Burnett, T. White, B.-Y. Nguyen, B. E. White, S. Venkatesan, J. Mogab, I. Cayrefourcq, and C. Mazure, "Strain-enhanced CMOS through novel process-substrate stress hybridization of super-critically thick strained silicon directly on insulator (SC-SSOI)," in VLSI Symp. Tech. Dig., 2006, pp. 130-131.
11. R. Pantel, S. Jullian, D. Dellile, D. Dutartre, A. Chantre, O. Kermarrec, Y. Campidelli, and L. F. T. Z. Kwakman, "Inelastic electron scattering observation using energy filtered transmission electron microscopy for silicon-germanium nanostructures imaging," Micron, vol.34, no.3-5, pp. 239-247, 2003.
12. C. Mourrain, B. Cretu, G. Ghibaudo, and P. Cottin, "New method for parameter extraction in deep sub-micrometer MOSFETs," in Proc. ICMTS, 2000, pp. 181-186.
13. A. Madan, G. Samudra, and Y.-C. Yeo, "Strain optimization in ultrathin body transistors with silicon-germanium source and drain stressors," J. Appl. Phys., vol.104, no.8, pp. 084505-1-084505-5, Oct. 2008.