Strain-enhanced CMOS through novel process-substrate stress hybridization of super-critically thick strained silicon directly on insulator (SC-SSOI)

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2006, Pages 130-131

  Thean, A V Y ^a   Zhang, D ^a   Vartanian, V ^a   Adams, V ^a   Conner, J ^a   Canonico, M ^a   Desjardin, H ^a   Grudowski, P ^a   Gu, B ^a   Shi, Z H ^a   Murphy, S ^a   Spencer, G ^a   Filipiak, S ^a   Goedeke, D ^a   Wang, X D ^a   Goolsby, B ^a   Dhandapani, V ^a   Prabhu, L ^a   Backer, S ^a   La, L B ^a   Burnett, D ^a   White, T ^a   Nguyen, B Y ^a   White, B E ^a   Venkatesan, S ^a   Mogab, J ^a   Cayrefourcq, I ^b   Mazure, C ^b   more..

^a FREESCALE SEMICONDUCTOR INC   (United States)

^b PARC TECHNOLOGIQUE DES FONTAINES   (France)

Author keywords

[No Author keywords available]

Indexed keywords

LEAKAGE CURRENTS; SEMICONDUCTING SILICON COMPOUNDS; SILICON ON INSULATOR TECHNOLOGY; STRAIN MEASUREMENT; STRESS ANALYSIS;

GATE LEAKAGE CURRENTS; PROCESS COMPLEXITY; STRESS HYBRIDIZATION;

CMOS INTEGRATED CIRCUITS;

EID: 41149110161     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. Thean et. al., Symp. VLSI Tech. Dig. p.134, 2005.
2. Thean et. al., IEDM Tech. Dig. 2005.
3. Ota et. al., Symp. VLSI Tech. Dig. P. 138, 2005
4. Zhang et. al., Symp. VLSI Tech. Dig. p. 27, 2005.