N-channel MOSFETs fabricated on SiGe dots for strain-enhanced mobility

IEEE Electron Device Letters

Volumn 31, Issue 10, 2010, Pages 1083-1085

  Jovanovic, V ^a   Biasotto, C ^a   Nanver, L K ^a   Moers, J ^b   Grutzmacher, D ^b   Gerharz, J ^b   Mussler, G ^b   Van Der Cingel, J ^a   Zhang, J J ^c   Bauer, G ^c   Schmidt, O G ^d   Miglio, L ^e  

^a DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

^b FORSCHUNGSZENTRUM JÜLICH   (Germany)

^c JOHANNES KEPLER UNIVERSITY LINZ   (Austria)

^d IFW DRESDEN   (Germany)

^e UNIVERSITY OF MILANO BICOCCA   (Italy)

Author keywords

CMOS; excimer laser annealing (ELA); low temperature gate stack; SiGe; strain enhanced mobility; StranskiKrastanow (SK) growth mode; ultrashallow source drain junctions

Indexed keywords

CMOS; EXCIMER LASER ANNEALING; GROWTH MODES; LOW TEMPERATURES; SIGE; SOURCE/DRAIN JUNCTIONS;

ANNEALING; DRAIN CURRENT; GERMANIUM; LOGIC GATES; MOS DEVICES; SEMICONDUCTING SILICON; SEMICONDUCTING SILICON COMPOUNDS; SILICON ALLOYS;

TENSILE STRAIN;

EID: 77957581405     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2010.2058995     Document Type: Article

References (15)

1. P. Packan, S. Akbar, M. Armstrong, D. Bergstrom, M. Brazier, H. Deshpande, K. Dev, G. Ding, T. Ghani, O. Golonzka, W. Han, J. He, R. Heussner, R. James, J. Jopling, C. Kenyon, S.-H. Lee, M. Liu, S. Lodha, B.Mattis, A.Murthy, L. Neiberg, J. Neirynck, S. Pae, C. Parker, L. Pipes, J. Sebastian, J. Seiple, B. Sell, A. Sharma, S. Sivakumar, B. Song, A. St. Amour, K. Tone, T. Troeger, C. Weber, K. Zhang, Y. Luo, and S. Natarajan, "High performance 32 nm logic technology featuring 2nd generation high-k + metal gate transistors," in IEDM Tech. Dig., 2009, pp. 659-662.
2. R. A. Donaton, D. Chidambarrao, J. Johnson, P. Chang, Y. Liu, W. K. Henson, J. Holt, X. Li, J. Li, A. Domenicucci, A. Madan, K. Rim, and C. Wann, "Design and fabrication of MOSFETs with a reverse embedded SiGe (Rev. e-SiGe) structure," in IEDM Tech. Dig., 2006, pp. 1-4.
3. K.-W. Ang, C.-H. Tung, N. Balasubramanian, G. S. Samudra, and Y.-C. Yeo, "Strained n-channel transistors with silicon source and drain regions and embedded silicon/germanium as strain-transfer structure," IEEE Electron Device Lett., vol.28, no.7, pp. 609-612, Jul. 2007.
4. O. G. Schmidt and K. Eberl, "Self-assembled Ge/Si dots for faster field-effect transistors," IEEE Trans. Electron Devices, vol.48, no.6, pp. 1175-1179, Jun. 2001.
5. J. J. Zhang, M. Stoffel, A. Rastelli, O. G. Schmidt, V. Jovanovíc, L. K. Nanver, and G. Bauer, "SiGe growth on patterned Si(001): Surface evolution and evidence of modified island coarsening," Appl. Phys. Lett., vol.91, no.17, p. 173 115, Oct. 2007.
6. T. U. Schlli, G. Vastola, M.-I. Richard, A. Malachias, G. Renaud, F. Uhlk, F. Montalenti, G. Chen, L. Miglio, F. Schffler, and G. Bauer, "Enhanced relaxation and intermixing in Ge islands grown on pitpatterned Si(001)," Phys. Rev. Lett., vol.102, no.2, p. 025 502, Jan. 2009.
7. E. Bonera, F. Pezzoli, A. Picco, G. Vastola, M. Stoffel, E. Grilli, M. Guzzi, A. Rastelli, O. G. Schmidt, and L. Miglio, "Strain in a single ultrathin silicon layer on top of SiGe islands: Raman spectroscopy and simulations," Phys. Rev. B, Condens. Matter, vol.79, no.7, p. 075 321, Feb. 2009.
8. N. Hrauda, J. J. Zhang, J. Stangl, A. Rehman-Khan, G. Bauer, M. Stoffel, O. G. Schmidt, V. Jovanovíc, and L. K. Nanver, "X-ray investigation of buried SiGe islands for devices with strain-enhanced mobility," J. Vac. Sci. Technol. B, Microelectron. Nanometer Struct., vol.27, no.2, pp. 912-918, Mar. 2009.
9. G. S. Kar, S. Kiravittaya, U. Denker, B.-Y. Nguyen, and O. G. Schmidt, "Strain distribution in a transistor using self-assembled SiGe islands in source and drain regions," Appl. Phys. Lett., vol.88, no.25, p. 253 108, Jun. 2006.
10. S. Frégonse, J. Zhuang, and J. N. Burghartz, "Modeling of strained CMOS on disposable SiGe dots: Strain impacts on devices electrical characteristics," IEEE Trans. Electron Devices, vol.54, no.9, pp. 2321-2326, Sep. 2007.
11. M. Jurczak, T. Skotnicki, M. Paoli, B. Tormen, J. Martins, J. L. Regolini, D. Dutartre, P. Ribot, D. Lenoble, R. Pantel, and S. Monfray, "Siliconon-nothing (SON)-An innovative process for advanced CMOS," IEEE Trans. Electron Devices, vol.47, no.11, pp. 2179-2187, Nov. 2000.
12. C. Biasotto, V. Jovanovíc, V. Gonda, J. van der Cingel, S. Milosavljevíc, and L. K. Nanver, "Integration of laser-annealed junctions in a lowtemperature high-k metal-gate MISFET," in Proc. ULIS Conf., 2009, pp. 181-184.
13. S. Dhar, H. Kosina, V. Palankovski, S. E. Ungersboeck, and S. Selberherr, "Electron mobility model for strained-Si devices," IEEE Trans. Electron Devices, vol.52, no.4, pp. 527-533, Apr. 2005.
14. V. Gonda, A. Burtsev, T. L. M. Scholtes, and L. K. Nanver, "Near-ideal implanted shallow-junction diode formation by excimer laser annealing," in Proc. RTP, 2005, pp. 93-100.
15. V. Jovanovíc, T. Suligoj, M. Poljak, Y. Civale, and L. K. Nanver, "Ultrahigh aspect-ratio FinFET technology," Solid State Electron., vol.54, no.9, pp. 870-876, Sep. 2010, article in press.