A CMOS IC for Gb/s viterbi decoding: System design and VLSI implementation

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 4, Issue 1, 1996, Pages 17-31

  Dawid, Herbert ^a,b,c   Fettweis, Gerhard ^d   Meyr, Heinrich ^b  

^a IEEE

^b RWTH AACHEN UNIVERSITY   (Germany)

^c Synopsys Design and Consulting   (Germany)

^d DRESDEN UNIVERSITY OF TECHNOLOGY   (Germany)

Author keywords

Channel decoding; Minimized method; Parallel architecture; Viterbi algorithm; Viterbi decoder; VLSI

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMMUNICATION CHANNELS (INFORMATION THEORY); COMPUTATIONAL METHODS; CONVOLUTIONAL CODES; DATA COMMUNICATION SYSTEMS; DECODING; INTEGRATED CIRCUIT MANUFACTURE; PARALLEL ALGORITHMS; RECURSIVE FUNCTIONS; SYSTEMS ANALYSIS; TRELLIS CODES; VLSI CIRCUITS;

ADD COMPARE SELECT RECURSION; CHANNEL DECODING; MINIMIZED METHOD; PARALLEL ARCHITECTURE; VITERBI ALGORITHM; VITERBI DECODING;

CMOS INTEGRATED CIRCUITS;

EID: 0030107682     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.486078     Document Type: Article

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