Performance yield-driven task allocation and scheduling for MPSoCs under process variation

Proceedings - Design Automation Conference

Volumn , Issue , 2010, Pages 326-331

  Huang, Lin ^a   Xu, Qiang ^a  

^a CHINESE UNIVERSITY OF HONG KONG   (Hong Kong)

Author keywords

Performance yield; Process variation; Task scheduling

Indexed keywords

ACCURATE PERFORMANCE; CMOS TECHNOLOGY; DESIGN STAGE; EXECUTION TIME; MULTI PROCESSOR SYSTEMS; PERFORMANCE ANALYSIS; PERFORMANCE YIELD; PROCESS VARIATION; QUASI-STATIC SCHEDULING; RUNTIMES; SPATIAL CORRELATIONS; SYSTEMATIC VARIATION; TASK ALLOCATION AND SCHEDULING; TASK SCHEDULE; TASK-SCHEDULING; TIMING CONSTRAINTS; YIELD ESTIMATION;

CMOS INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; MULTIPROCESSING SYSTEMS; MULTITASKING; TIMING CIRCUITS;

SCHEDULING ALGORITHMS;

EID: 77956201399     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1837274.1837358     Document Type: Conference Paper

References (21)

1. T. Adam, K. Chandy, and J. Dickson. A Comparison of List Scheduling for Parallel Processing Systems. Communications of the ACM, 17(12):685-690, December 1974.
2. A. Agarwal, D. Blaauw, and V. Zolotov. Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations. In Proc. ICCAD, pages 900-907, 2003.
3. P. Bjorn-Jorgensen and J. Madsen. Critical Path Driven Cosynthesis for Heterogeneous Target Architectures. In Proc. International Conference on Hardware Software Codesign, pages 15-19, 1997.
4. S. Borkar et al. Parameter Variations and Impact on Circuits and Microarchitecture. In Proc. DAC, pages 338-342, 2003.
5. T. D. Braun, H. J. Siegel, N. Beck, L. L. Boloni, M. Maheswaran, A. I. Reuther, J. P. Robertson, M. D. Theys, B. Yao, D. Hensgen, and R. F. Freund. A comparison of eleven static heuristics for mapping a class of independent tasks onto heterogeneous distributed computing systems. Journal of Parallel and Distributed Computing, 61(6):810-837, June 2001.
6. H. Chon and T. Kim. Timing Variation-Aware Task Scheduling and Binding for MPSoC. In Proc. ASP-DAC, pages 137-142, 2009.
7. R. P. Dick, D. L. Rhodes, and W. Wolf. TGFF: Task Graphs for Free. Pages 97-101, 1998.
8. S. Haykin. In Neural Networks and Learning Machines. Prentice-Hall, 3rd edition, 2008.
9. S. Herbert and D. Marculescu. Characterizing Chip-Multiprocessor Variability-Tolerance. In Proc. DAC, pages 313-318, 2008.
10. L. Huang, F. Yuan, and Q. Xu. Lifetime Reliability-Aware Task Allocation and Scheduling for MPSoC Platforms. In Proc. DATE, 2009.
11. P. Jäckel. In Monte Carlo Methods in Finance. John Wiley & Sons, 2002.
12. Y.-K. Kwok and I. Ahmad. Static task scheduling and allocation algorithms for scalable parallel and distributed systems: Classification and performance comparison. In Y. C. Kwong, editor, Annual Review of Scalable Computing, pages 107-227. 2000.
13. X. Liang, G.-Y. Wei, and D. Brooks. ReVIVaL: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency. In Proc. ISCA, pages 191-202, 2008.
14. S. Nassif. Delay Variability: Sources, Impacts and Trends. In Proc. ISSCC, pages 368-369, 2000.
15. S. R. Sarangi, B. Greskamp, R. Teodorescu, J. Nakano, A. Tiwari, and J. Torrellas. Varius: A model of process variation and resulting timing errors for microarchitects. IEEE Transactions on Semiconductor Manufacturing, 21(1):3-13, February 2008.
16. SIA. International Technology Roadmap for Semiconductors. http://public.itrs.net.
17. L. Singhal and E. Bozorgzadeh. Process Variation Aware System-Level Task Allocation Using Stochastic Ordering of Delay Distributions. In Proc. ICCAD, pages 570-574, 2008.
18. B. E. Stine, D. S. Boning, and J. E. Chung. Analysis and Decomposition of Spatial Variation in Integrated Circuit Processes and Devices. IEEE Transactions on Semiconductor Manufacturing, 10(1):24-41, Feb. 1997.
19. P.-N. Tan, M. Steinbach, and V. Kumar. In Introduction to Data Mining. Addison-Wesley, 2006.
20. F. Wang, C. Nicopoulos, X. Wu, Y. Xie, and N. Vijaykrishnan. Variation-Aware Task Allocation and Scheduling for MPSoC. In Proc. ICCAD, pages 598-603, 2007.
21. F. Wang, X. Wu, and Y. Xie. Variability-Driven Module Selection with Joint Design Time Optimization and Post-Silicon Tuning. In Proc. ASP-DAC, pages 2-9, 2008.