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Volumn , Issue , 2008, Pages 570-574

Process variation aware system-level task allocation using stochastic ordering of delay distributions

Author keywords

[No Author keywords available]

Indexed keywords

ALLOCATING TASKS; AWARE SYSTEMS; BENCHMARK SUITES; DELAY DISTRIBUTIONS; EFFECTIVE PERFORMANCES; EFFICIENT COMPUTATIONS; EXECUTION TIMES; MAXIMUM OPERATING FREQUENCIES; OPTIMALITY; PROBABILISTIC SOLUTIONS; PROCESS TECHNOLOGIES; PROCESS VARIATIONS; STOCHASTIC ANALYSES; STOCHASTIC ORDERINGS; SYSTEM LEVELS; TASK ALLOCATIONS;

EID: 57849087718     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2008.4681633     Document Type: Conference Paper
Times cited : (19)

References (12)
  • 1
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    • Feb
    • K. A. Bowman, S. G. Duvall, and J. D. Meindl, "Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration," IEEE Journal of Solid State Circuit, vol. 37, no. 2, Feb. 2002.
    • (2002) IEEE Journal of Solid State Circuit , vol.37 , Issue.2
    • Bowman, K.A.1    Duvall, S.G.2    Meindl, J.D.3
  • 2
    • 57849095968 scopus 로고    scopus 로고
    • Timing variation-aware high-level synthesis
    • J. Jung and T. Kim, "Timing variation-aware high-level synthesis," in IEEE ICCAD, 2007, pp. 317-321.
    • (2007) IEEE ICCAD , pp. 317-321
    • Jung, J.1    Kim, T.2
  • 4
    • 57849153191 scopus 로고    scopus 로고
    • Variability-driven module selection with joint design time optimization and post-silicon tuning
    • F. Wang, X. Wu, and Y. Xie, "Variability-driven module selection with joint design time optimization and post-silicon tuning," in IEEE ASPDAC, 2008.
    • (2008) IEEE ASPDAC
    • Wang, F.1    Wu, X.2    Xie, Y.3
  • 5
    • 46149102490 scopus 로고    scopus 로고
    • System level process-driven variability analysis for single and multiple voltage-frequency island systems
    • Nov
    • D. Marculescu and S. Garg, "System level process-driven variability analysis for single and multiple voltage-frequency island systems," in IEEE Intl. Conference on Computer Aided Design (ICCAD), Nov. 2006.
    • (2006) IEEE Intl. Conference on Computer Aided Design (ICCAD)
    • Marculescu, D.1    Garg, S.2
  • 6
    • 57849088921 scopus 로고    scopus 로고
    • Buffer insertion under process variations for delay minimization
    • L. Deng and M. Wong, "Buffer insertion under process variations for delay minimization," in IEEE ICCAD, 2005.
    • (2005) IEEE ICCAD
    • Deng, L.1    Wong, M.2
  • 9
    • 34548304812 scopus 로고    scopus 로고
    • System level process variation driven throughput analysis for single and multiple voltage-frequency island designs
    • Apr
    • S. Garg and D. Marculescu, "System level process variation driven throughput analysis for single and multiple voltage-frequency island designs," in IEEE Design, Automation and Test in Europe Conference (DATE), Apr. 2007.
    • (2007) IEEE Design, Automation and Test in Europe Conference (DATE)
    • Garg, S.1    Marculescu, D.2
  • 10
    • 67650691171 scopus 로고    scopus 로고
    • Placement and timing for fpgas considering variations
    • Y. Lin, M. Hutton, and L. He, "Placement and timing for fpgas considering variations," in IEEE FPL, 2006.
    • (2006) IEEE FPL
    • Lin, Y.1    Hutton, M.2    He, L.3
  • 12
    • 0033729527 scopus 로고    scopus 로고
    • A hierarchical approach for bounding the completion time distribution of stochastic task graphs
    • M. Colajanni, F. L. Presti, and S. Tucci, "A hierarchical approach for bounding the completion time distribution of stochastic task graphs," Performance Evaluation, vol. 41, no. 1, 2000.
    • (2000) Performance Evaluation , vol.41 , Issue.1
    • Colajanni, M.1    Presti, F.L.2    Tucci, S.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.