-
1
-
-
3042515336
-
Synthesis of reversible logic
-
Paris, France, Febr.
-
A. Agrawal, and N.K. Jha, Synthesis of reversible logic, Proc. DATE, Paris, France, Febr. 2004, pp. 1530-1591
-
(2004)
Proc. DATE
, pp. 1530-1591
-
-
Agrawal, A.1
Jha, N.K.2
-
3
-
-
42149155654
-
Reversible logic synthesis with fredkin and peres gates
-
Article 2, March
-
J. Donald and N.K. Jha, Reversible Logic Synthesis with Fredkin and Peres Gates, ACM Journal on Emerging Technologies in Computing Systems, Vol. 4, No. 1, Article 2, March 2008.
-
(2008)
ACM Journal on Emerging Technologies in Computing Systems
, vol.4
, Issue.1
-
-
Donald, J.1
Jha, N.K.2
-
4
-
-
0141856026
-
Reversible function synthesis with minimum garbage outputs
-
Trier, Germany, March
-
G. W. Dueck and D. Maslov, "Reversible Function Synthesis with Minimum Garbage Outputs," 6th International Symposium on Representations and Methodology of Future Computing Technologies (RM), Trier, Germany, March 2003, pp. 154-161.
-
(2003)
6th International Symposium on Representations and Methodology of Future Computing Technologies (RM)
, pp. 154-161
-
-
Dueck, G.W.1
Maslov, D.2
-
5
-
-
34748876694
-
Exact toffoli network synthesis of reversible logic using boolean satisfiability
-
D. Große, X. Chen, and R. Drechsler, Exact Toffoli network synthesis of reversible logic using boolean satisfiability, Proc. IEEE Dallas/CAS Workshop, pp. 51-54, 2006.
-
(2006)
Proc. IEEE Dallas/CAS Workshop
, pp. 51-54
-
-
Große, D.1
Chen, X.2
Drechsler, R.3
-
6
-
-
77955188604
-
Exact multiple control toffoli network synthesis with SAT techniques
-
D. Große, R. Wille, G.W. Dueck, and R. Drechsler. Exact multiple control toffoli network synthesis with SAT techniques. IEEE Trans. on CAD, 28(5):703-715, 2009.
-
(2009)
IEEE Trans. on CAD
, vol.28
, Issue.5
, pp. 703-715
-
-
Große, D.1
Wille, R.2
Dueck, G.W.3
Drechsler, R.4
-
7
-
-
33750588847
-
An algorithm for synthesis of reversible logic circuits
-
P. Gupta, A. Agrawal, and N. Jha. An algorithm for synthesis of reversible logic circuits. IEEE Trans. on CAD, 25(11):pp. 2317-2330, 2006.
-
(2006)
IEEE Trans. on CAD
, vol.25
, Issue.11
, pp. 2317-2330
-
-
Gupta, P.1
Agrawal, A.2
Jha, N.3
-
10
-
-
4444239912
-
A new heuristic algorithm for reversible logic synthesis
-
June
-
P. Kerntopf, A new heuristic algorithm for reversible logic synthesis, Proc. DAC, pp. 834-837, June 2004.
-
(2004)
Proc. DAC
, pp. 834-837
-
-
Kerntopf, P.1
-
11
-
-
0348183556
-
Reversible logic synthesis by gate composition
-
A. Khlopotine, M. Perkowski, and P. Kerntopf, Reversible logic synthesis by gate composition, Proc. IWLS 2002, pp. 261 - 266.
-
(2002)
Proc. IWLS
, pp. 261-266
-
-
Khlopotine, A.1
Perkowski, M.2
Kerntopf, P.3
-
12
-
-
77955327443
-
Realization of incompletely specified functions in minimized reversible circuits
-
M. Kumar, B. Year, N. Metzger, Y. Wang, and M. Perkowski, Realization of Incompletely Specified Functions in Minimized Reversible Circuits, Proc. RM 2007.
-
(2007)
Proc. RM
-
-
Kumar, M.1
Year, B.2
Metzger, N.3
Wang, Y.4
Perkowski, M.5
-
14
-
-
0346392713
-
Improved quantum cost for k-bit toffoli gates
-
Dec.
-
D. Maslov and G. Dueck, Improved quantum cost for k-bit Toffoli gates, IEE Electron. Lett., vol. 39, no. 25, pp. 1790-1791, Dec. 2003.
-
(2003)
IEE Electron. Lett
, vol.39
, Issue.25
, pp. 1790-1791
-
-
Maslov, D.1
Dueck, G.2
-
17
-
-
8344281996
-
Reversible cascades with minimal garbage
-
November
-
D. Maslov and G.W. Dueck, Reversible cascades with minimal garbage, IEEE Transactions on CAD, 23(11): pp. 497-1509, November 2004.
-
(2004)
IEEE Transactions on CAD
, vol.23
, Issue.11
, pp. 497-1509
-
-
Maslov, D.1
Dueck, G.W.2
-
18
-
-
35148830918
-
Techniques for the synthesis of reversible toffoli networks
-
Article 42, Sept.
-
D. Maslov, G.W. Dueck, and D.M. Miller, Techniques for the Synthesis of Reversible Toffoli Networks, ACM Transactions on Design Automation of Electronic Systems, Vol. 12, No. 4, Article 42, Sept. 2007.
-
(2007)
ACM Transactions on Design Automation of Electronic Systems
, vol.12
, Issue.4
-
-
Maslov, D.1
Dueck, G.W.2
Miller, D.M.3
-
19
-
-
39749119848
-
-
IEEE Trans. on CAD March
-
D. Maslov, G.W. Dueck, D. M. Miller, and C. Negrevergne, Quantum Circuit Simplification and Level Compaction, IEEE Trans. on CAD, Vol. 27, No. 3, March 2008, pp 436-444.
-
(2008)
Quantum Circuit Simplification and Level Compaction
, vol.27
, Issue.3
, pp. 436-444
-
-
Maslov, D.1
Dueck, G.W.2
Miller, D.M.3
Negrevergne, C.4
-
20
-
-
77955328969
-
-
Web Page
-
D. Maslov, Web Page: http://webhome.cs.uvic.ca/~dmaslov/
-
-
-
Maslov, D.1
-
21
-
-
0347554023
-
Spectral techniques for reversible logic synthesis
-
D. M. Miller and G.W. Dueck, Spectral Techniques for Reversible Logic Synthesis, Proc. RM 2003, pp. 56-62.
-
(2003)
Proc. RM
, pp. 56-62
-
-
Miller, D.M.1
Dueck, G.W.2
-
22
-
-
0043136670
-
A transformation based algorithm for reversible logic synthesis
-
Anaheim June
-
D. M. Miller, D. Maslov and G. W. Dueck, A Transformation Based Algorithm for Reversible Logic Synthesis, Proc. DAC, Anaheim, pp. 318-323, June 2003.
-
(2003)
Proc. DAC
, pp. 318-323
-
-
Miller, D.M.1
Maslov, D.2
Dueck, G.W.3
-
23
-
-
0012928469
-
Fast heuristic minimization of exclusive sum-of-products
-
Starkville, Mississippi
-
A. Mishchenko and M. Perkowski, Fast Heuristic Minimization of Exclusive Sum-of-Products, Proc. Reed-Muller Workshop, 2001, Starkville, Mississippi, pp. 242-250.
-
(2001)
Proc. Reed-Muller Workshop
, pp. 242-250
-
-
Mishchenko, A.1
Perkowski, M.2
-
24
-
-
0348183555
-
Logic synthesis of reversible wave cascades
-
June 4-7
-
A. Mishchenko and M. Perkowski, "Logic Synthesis of Reversible Wave Cascades", Proc. IEEE/ACM IWLS, June 4-7, 2002, pp. 197 - 202.
-
(2002)
Proc. IEEE/ACM IWLS
, pp. 197-202
-
-
Mishchenko, A.1
Perkowski, M.2
-
25
-
-
52549094794
-
Heuristic methods to use don't cares in automated design of reversible and quantum logic circuits
-
M. Mohamadi, and M. Eshghi, Heuristic methods to use don't cares in automated design of reversible and quantum logic circuits. Quantum Inf. Process. J. 7(4), pp. 175-192, 2008.
-
(2008)
Quantum Inf. Process. J.
, vol.7
, Issue.4
, pp. 175-192
-
-
Mohamadi, M.1
Eshghi, M.2
-
26
-
-
77955313608
-
Synthesis of reversible circuits with small ancilla bits for large irreversible incompletely specified multi-output boolean functions
-
May 18 Calgary, Canada
-
Ch. Stedman, B. Yen and M. Perkowski, Synthesis of Reversible Circuits with Small Ancilla Bits for Large Irreversible Incompletely Specified Multi-Output Boolean Functions, Proc. 14th International Workshop on Post-Binary ULSI Systems, May 18, 2005, Calgary, Canada.
-
(2005)
Proc. 14th International Workshop on Post-Binary ULSI Systems
-
-
Stedman, C.1
Yen, B.2
Perkowski, M.3
-
27
-
-
77955311691
-
Gate cascade generation using ESOP minimization and QMDD-based swapping
-
May 23-24
-
J. E. Rice K. B. Fazel, M.A. Thornton, and K. B. Kent Toffoli Gate Cascade Generation Using ESOP Minimization and QMDD-based Swapping. Proc. RM, May 23-24, 2009, pp. 63-72.
-
(2009)
Proc. RM
, pp. 63-72
-
-
Rice, J.E.1
Fazel, K.B.2
Thornton, M.A.3
Kent Toffoli, K.B.4
-
28
-
-
50249119203
-
A novel synthesis algorithm for reversible circuits
-
San Jose, California
-
M. Saeedi, M. Sedighi, M. S. Zamani, A Novel Synthesis Algorithm for Reversible Circuits, Proc. ICCAD, San Jose, California, pp. 65-68. 2007.
-
(2007)
Proc. ICCAD
, pp. 65-68
-
-
Saeedi, M.1
Sedighi, M.2
Zamani, M.S.3
-
29
-
-
49549094423
-
A new methodology for quantum circuit synthesis: CNOT-based circuits as an example
-
Paradise Point Resort and Spa, San Diego, CA, USA, May 30-June 1
-
M. Saeedi, M. Sedighi, M. Saheb Zamani, A New Methodology for Quantum Circuit Synthesis: CNOT-Based Circuits as an Example," Proc. IWLS, 2007. Paradise Point Resort and Spa, San Diego, CA, USA, May 30-June 1.
-
(2007)
Proc. IWLS
-
-
Saeedi, M.1
Sedighi, M.2
Saheb Zamani, M.3
-
30
-
-
36348950128
-
On the behavior of substitution-based reversible circuit synthesis algorithms: Investigation and improvement
-
9-11 March
-
M. Saeedi, M. S. Zamani, M. Sedighi, On the Behavior of Substitution-Based Reversible Circuit Synthesis Algorithms: Investigation and Improvement," Proc. ISVLSI, 9-11 March 2007, pp. 428-436.
-
(2007)
Proc. ISVLSI
, pp. 428-436
-
-
Saeedi, M.1
Zamani, M.S.2
Sedighi, M.3
-
31
-
-
50449097451
-
RevLib: An online resource for reversible functions and reversible circuits
-
Dallas, TX, USA
-
th ISMVL, pp. 220-225. Dallas, TX, USA, 2008. http://www.revlib.org.
-
(2008)
th ISMVL
, pp. 220-225
-
-
Wille, R.1
Große, D.2
Teuber, L.3
Dueck, G.W.4
Drechsler, R.5
-
32
-
-
70350712413
-
BDD-based synthesis of reversible logic for large functions
-
San Francisco, California
-
R. Wille, R. Drechsler, BDD-based Synthesis of Reversible Logic for Large Functions. Proc. DAC, pp. 270-275. San Francisco, California
-
Proc. DAC
, pp. 270-275
-
-
Wille, R.1
Drechsler, R.2
-
33
-
-
80052048935
-
Synthesis of reversible functions beyond gate count and quantum cost
-
R. Wille, M. Saeedi, R. Drechsler, Synthesis of Reversible Functions Beyond Gate Count and Quantum Cost. IWLS 2009.
-
IWLS 2009
-
-
Wille, R.1
Saeedi, M.2
Drechsler, R.3
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