Studies on electrical performance and thermal stress of a silicon interposer with TSVs

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2010, Pages 1088-1093

  Sunohara, Masahiro ^a   Sakaguchi, Hideaki ^a   Takano, Akihito ^a   Arai, Rie ^a   Murayama, Kei ^a   Higashi, Mitsutoshi ^a  

^a SHINKO ELECTRIC INDUSTRIES CO LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

AIR-GAPS; CU WIRING; ELECTRICAL PERFORMANCE; FABRICATION PROCESS; FUSING CURRENT; GLOBAL WIRING; PIEZORESISTIVE SENSORS; RELIABILITY TEST; SILICON ETCHING; SILICON MODULES; SYSTEM ON CHIPS;

CUSTOMER SATISFACTION; PROGRAMMABLE LOGIC CONTROLLERS; STRESS RELIEF; THERMAL STRESS; THERMOELASTICITY;

ELECTRIC WIRING;

EID: 77955209503     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2010.5490837     Document Type: Conference Paper

References (15)

1. M.Sunohara et'al, "Silicon Interposer with TSVs and Fine Multi layer Wiring." in Proc. 58st ECTC, Frolida USA, May. 2008, pp. 848-852
2. K. Kumagai et'al, "A Silicon Interposer BGA Package with Cu-Filled TSV and Multi-Layer Cu-Plating Interconnect." in Proc. 58st ECTC, Frolida USA, May. 2008, pp. 571-576
3. M. Sunohara, "Development of Silicon Module with TSVs and Global Wiring (L/S=0.8/0.8um) " in Proc. 59st ECTC, San Diego, May. 2009, pp.25-31
4. K. Takahashi et'al, "Process integration of 3D chip stack with vertical interconnection." in Proc. 54stECTC, Las Vegas, June. 2004, pp. 601-609.
5. Michael W et'al, "Fabrication and electrical characterization of 3D vertical interconnects." in Proc. 56stECTC, San Diego, May. 2006, pp. 394-398
6. M.Sekiguchi et'al, "Novel low cost intergration of through chip interconnection and application to CMOS image sensor." in Proc. 56st ECTC, San Diego, May. 2006, pp. 1367-1374.
7. P. Ramm et'al, "Through silicon via technology-process and reliability for wafer lavel 3D system integration." in Proc. 58st ECTC, Frolida USA, May. 2008, pp. 841-846
8. Won Kyu Jeung et'al, "Reflowable ISM WLP." in Proc. 58st ECTC, Frolida USA, May. 2008, pp. 297-302
9. T. Mitsuhashi et'al, "Development of stacked memory chip process technology." in Proc. 8th VLSI packaging workshop., Kyoto, December 2006, pp. 125-128.
10. P.S. Andry et'al, "A CMOS compatible process for fabricating electrical through-vias in silicon." in Proc. 56stECTC, San Diego, May. 2006, pp. 831-837.
11. J.U. Knickerbockeret' al, "3D Silicon integration," in Proc. 58st ECTC, Frolida USA, May. 2008, pp. 538-543
12. M. Akazawa et'al, "High density packaging technology on silicon substrate.," in Proc. 53st ECTC, San Diego USA, May. 2003, pp. 647-651.
13. S. Yamamoto et'al, " Through hole interconnection technologies in Si substrate for wafer level package " in Proc. ICEP2006, Tokyo JPN, Apl.2006
14. K.N. Tu " Recent advance on elctromigration in very-large-scale- integration of interconnects " Jounal of appliedphysics. Volume 94 Number 9, Nov.2003
15. David et'al " In situ of the stress development during fabrication process of micro-assemblies" in Proc. 59st ECTC, San Diego, May. 2009, pp.117-124