Back Suction: Service guarantees for latency-sensitive on-chip networks

NOCS 2010 - The 4th ACM/IEEE International Symposium on Networks-on-Chip

Volumn , Issue , 2010, Pages 155-162

  Diemer, Jonas ^a   Ernst, Rolf ^a  

^a TECHNICAL UNIVERSITY OF BRAUNSCHWEIG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

BEST-EFFORT TRAFFIC; BUFFER OCCUPANCY; CONTROL SCHEMES; EXPERIMENTAL EVALUATION; FORMAL ANALYSIS; FORMAL SERVICE; GENERAL PURPOSE PROCESSORS; GUARANTEED SERVICE; MANY-CORE; NETWORKS ON CHIPS; ON-CHIP NETWORKS; REAL TIME REQUIREMENT; SERVICE GUARANTEES; STREAMING TRAFFIC; TRAFFIC REQUIREMENTS;

GENERAL PURPOSE COMPUTERS; MICROPROCESSOR CHIPS; ROUTERS;

QUALITY CONTROL;

EID: 77955107429     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NOCS.2010.38     Document Type: Conference Paper

References (18)

1. M. Kistler, M. Perrone, and F. Petrini, "Cell Multiprocessor Communication Network: Built for Speed," IEEE Micro, vol. 26, no. 3, 2006.
2. D. Wentzlaff et al., "On-Chip Interconnection Architecture of the Tile Processor," IEEE Micro, vol. 27, no. 5, 2007.
3. L. Howard et al., "A 48-Core IA-32 Message-Passing Processor with DVFS in 45nm CMOS," in ISSCC, February 2010, .
4. N. Muralimanohar and R. Balasubramonian, "Interconnect Design Considerations for Large NUCA Caches," in ISCA, vol. 35, no. 2, 2007, .
5. A. d. C. Lucas, H. Sahlbach, S. Whitty, S. Heithecker, and R. Ernst, "Application Development with the FlexWAFE Realtime Stream Processing Architecture for FPGAs," ACM Transactions on Embedded Computing Systems, vol. 9, no. 1, October 2009.
6. A. Kumar, L.-S. Peh, and N. K. Jha, "Token Flow Control," in MICRO, 2008, .
7. M. Millberg, E. Nilsson, R. Thid, and A. Jantsch, "Guaranteed Bandwidth using Looped Containers in Temporally Disjoint Networks within the Nostrum Network on Chip," in DATE, vol. 2, 2004, .
8. K. Goossens, J. Dielissen, and A. Radulescu, "Æthereal Network on Chip: Concepts, Architectures, and Implementations," IEEE DESIGN & TEST, vol. 22, no. 5, 2005.
9. T. Bjerregaard, "The MANGO Clockless Network-on-Chip: Concepts and Implementation," Ph.D. dissertation, IMM, Danmarks Tekniske Universitet, 2005.
10. E. Bolotin, I. Cidon, R. Ginosar, and A. Kolodny, "QNoC: QoS Architecture and Design Process for Network on Chip," J. Syst. Archit., vol. 50, no. 2-3, 2004.
11. M. A. A. Faruque, G. Weiss, and J. Henkel, "Bounded Arbitration Algorithm for QoS-Supported On-chip Communication," in CODES+ISSS, 2006, .
12. T. M. Marescaux, "Mapping and Management of Communication Services on MP-SoC Platforms," Ph.D. dissertation, TU Eindhoven, 2007.
13. J. Lee, M. C. Ng, and K. Asanovic, "Globally-Synchronized Frames for Guaranteed Quality-of-Service in On-Chip Networks," in ISCA, 2008, .
14. J. Diemer, R. Ernst, and M. Kauschke, "Efficient Throughput-Guarantees for Latency-Sensitive Networks-On-Chip," in ASP-DAC, 2010, .
15. S. Schliecker, J. Rox, M. Negrean, K. Richter, M. Jersak, and R. Ernst, "System Level Performance Analysis for Real-Time Automotive Multi- Core and Network Architectures," IEEE Trans. CAD, vol. 28, no. 7, 2009.
16. J. Le Boudec and P. Thiran, Network Calculus: A Theory of Deterministic Queuing Systems for the Internet. Springer, 2001.
17. W. Dally, Principles and Practices of Interconnection Networks. Morgan Kaufmann, 2004.
18. S. Schliecker, M. Negrean, and R. Ernst, "Reliable Performance Analysis of a Multicore Multithreaded System-On-Chip (with appendix)," Technische Universität Braunschweig, Tech. Rep. 22837, 2008.