-
1
-
-
33746923043
-
Cell multiprocessor communication network: Built for speed
-
M. Kistler, M. Perrone, and F. Petrini, "Cell Multiprocessor Communication Network: Built for Speed," IEEE Micro, vol. 26, no. 3, 2006.
-
(2006)
IEEE Micro
, vol.26
, Issue.3
-
-
Kistler, M.1
Perrone, M.2
Petrini, F.3
-
2
-
-
36849030305
-
On-chip interconnection architecture of the tile processor
-
D. Wentzlaff et al., "On-Chip Interconnection Architecture of the Tile Processor," IEEE Micro, vol. 27, no. 5, 2007.
-
(2007)
IEEE Micro
, vol.27
, Issue.5
-
-
Wentzlaff, D.1
-
3
-
-
77952123736
-
A 48-core IA-32 message-passing processor with DVFS in 45nm CMOS
-
February
-
L. Howard et al., "A 48-Core IA-32 Message-Passing Processor with DVFS in 45nm CMOS," in ISSCC, February 2010, .
-
(2010)
ISSCC
-
-
Howard, L.1
-
4
-
-
35348847741
-
Interconnect design considerations for large NUCA caches
-
N. Muralimanohar and R. Balasubramonian, "Interconnect Design Considerations for Large NUCA Caches," in ISCA, vol. 35, no. 2, 2007, .
-
(2007)
ISCA
, vol.35
, Issue.2
-
-
Muralimanohar, N.1
Balasubramonian, R.2
-
5
-
-
70449389961
-
Application development with the FlexWAFE realtime stream processing architecture for FPGAs
-
October
-
A. d. C. Lucas, H. Sahlbach, S. Whitty, S. Heithecker, and R. Ernst, "Application Development with the FlexWAFE Realtime Stream Processing Architecture for FPGAs," ACM Transactions on Embedded Computing Systems, vol. 9, no. 1, October 2009.
-
(2009)
ACM Transactions on Embedded Computing Systems
, vol.9
, Issue.1
-
-
Lucas, A.D.C.1
Sahlbach, H.2
Whitty, S.3
Heithecker, S.4
Ernst, R.5
-
7
-
-
3042740415
-
Guaranteed bandwidth using looped containers in temporally disjoint networks within the nostrum network on chip
-
M. Millberg, E. Nilsson, R. Thid, and A. Jantsch, "Guaranteed Bandwidth using Looped Containers in Temporally Disjoint Networks within the Nostrum Network on Chip," in DATE, vol. 2, 2004, .
-
(2004)
DATE
, vol.2
-
-
Millberg, M.1
Nilsson, E.2
Thid, R.3
Jantsch, A.4
-
8
-
-
27344456043
-
Æthereal network on chip: Concepts, architectures, and implementations
-
K. Goossens, J. Dielissen, and A. Radulescu, "Æthereal Network on Chip: Concepts, Architectures, and Implementations," IEEE DESIGN & TEST, vol. 22, no. 5, 2005.
-
(2005)
IEEE Design & Test
, vol.22
, Issue.5
-
-
Goossens, K.1
Dielissen, J.2
Radulescu, A.3
-
10
-
-
1242309790
-
QNoC: QoS architecture and design process for network on chip
-
E. Bolotin, I. Cidon, R. Ginosar, and A. Kolodny, "QNoC: QoS Architecture and Design Process for Network on Chip," J. Syst. Archit., vol. 50, no. 2-3, 2004.
-
(2004)
J. Syst. Archit.
, vol.50
, Issue.2-3
-
-
Bolotin, E.1
Cidon, I.2
Ginosar, R.3
Kolodny, A.4
-
11
-
-
34547217982
-
Bounded arbitration algorithm for QoS-supported on-chip communication
-
M. A. A. Faruque, G. Weiss, and J. Henkel, "Bounded Arbitration Algorithm for QoS-Supported On-chip Communication," in CODES+ISSS, 2006, .
-
(2006)
CODES+ISSS
-
-
Faruque, M.A.A.1
Weiss, G.2
Henkel, J.3
-
13
-
-
52649094492
-
Globally-synchronized frames for guaranteed quality-of-service in on-chip networks
-
J. Lee, M. C. Ng, and K. Asanovic, "Globally-Synchronized Frames for Guaranteed Quality-of-Service in On-Chip Networks," in ISCA, 2008, .
-
(2008)
ISCA
-
-
Lee, J.1
Ng, M.C.2
Asanovic, K.3
-
14
-
-
77951244347
-
Efficient throughput-guarantees for latency-sensitive networks-on-chip
-
J. Diemer, R. Ernst, and M. Kauschke, "Efficient Throughput-Guarantees for Latency-Sensitive Networks-On-Chip," in ASP-DAC, 2010, .
-
(2010)
ASP-DAC
-
-
Diemer, J.1
Ernst, R.2
Kauschke, M.3
-
15
-
-
67650921132
-
System level performance analysis for real-time automotive multi- core and network architectures
-
S. Schliecker, J. Rox, M. Negrean, K. Richter, M. Jersak, and R. Ernst, "System Level Performance Analysis for Real-Time Automotive Multi- Core and Network Architectures," IEEE Trans. CAD, vol. 28, no. 7, 2009.
-
(2009)
IEEE Trans. CAD
, vol.28
, Issue.7
-
-
Schliecker, S.1
Rox, J.2
Negrean, M.3
Richter, K.4
Jersak, M.5
Ernst, R.6
-
18
-
-
63349104133
-
Reliable performance analysis of a multicore multithreaded system-on-chip (with appendix)
-
S. Schliecker, M. Negrean, and R. Ernst, "Reliable Performance Analysis of a Multicore Multithreaded System-On-Chip (with appendix)," Technische Universität Braunschweig, Tech. Rep. 22837, 2008.
-
(2008)
Technische Universität Braunschweig, Tech. Rep.
, pp. 22837
-
-
Schliecker, S.1
Negrean, M.2
Ernst, R.3
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